Silicon Laboratories C8051F346 SFR Definition 15.2. XBR1 Port I/O Crossbar Register, URT1E

C8051F340/1/2/3/4/5/6/7

SFR Definition 15.2. XBR1: Port I/O Crossbar Register 1

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

WEAKPUD	XBARE	T1E	T0E	ECIE		PCA0ME
Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0

00000000

SFR Address:

	0xE2
Bit7:	WEAKPUD: Port I/O Weak Pull-up Disable.
	0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input or
	push-pull output).
	1: Weak Pull-ups disabled.
Bit6:	XBARE: Crossbar Enable.
	0: Crossbar disabled; all Port drivers disabled.
	1: Crossbar enabled.
Bit5:	T1E: T1 Enable
	0: T1 unavailable at Port pin.
	1: T1 routed to Port pin.
Bit4:	T0E: T0 Enable
	0: T0 unavailable at Port pin.
	1: T0 routed to Port pin.
Bit3:	ECIE: PCA0 External Counter Input Enable
	0: ECI unavailable at Port pin.
	1: ECI routed to Port pin.
Bits2–0:	PCA0ME: PCA Module I/O Enable Bits.
	000: All PCA I/O unavailable at Port pins.
	001: CEX0 routed to Port pin.
	010: CEX0, CEX1 routed to Port pins.
	011: CEX0, CEX1, CEX2 routed to Port pins.
	100: CEX0, CEX1, CEX2, CEX3 routed to Port pins.
	101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins.
	110: Reserved.
	111: Reserved.

SFR Definition 15.3. XBR2: Port I/O Crossbar Register 2

R/W		R/W	R/W	R/W	R/W	R/W	R/W	R/W	Reset Value
								URT1E	00000000
Bit7		Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0	SFR Address:
									0xE3
Bits7–1:	RESERVED: Always write to 0000000b
Bit0:	URT1E: UART1 I/O Output Enable (C8051F340/1/4/5 Only)
	0: UART1 I/O unavailable at Port pins.
	1: UART1 TX1, RX1 routed to Port pins.

Rev. 0.5 153