C8051F340/1/2/3/4/5/6/7

SFR Definition 17.1. SMB0CF: SMBus Clock/Configuration

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

Reset Value

ENSMB

INH

BUSY

EXTHOLD SMBTOE

SMBFTE

SMBCS1

SMBCS0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

 

 

 

 

 

 

 

SFR Address: 0xC1

Bit7:

ENSMB: SMBus Enable.

 

 

 

 

 

 

This bit enables/disables the SMBus interface. When enabled, the interface constantly mon-

 

itors the SDA and SCL pins.

 

 

 

 

0:SMBus interface disabled.

1:SMBus interface enabled.

Bit6:

INH: SMBus Slave Inhibit.

 

 

 

When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events

 

occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are

 

not affected.

 

 

 

 

 

0: SMBus Slave Mode enabled.

 

1: SMBus Slave Mode inhibited.

Bit5:

BUSY: SMBus Busy Indicator.

 

This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0

 

when a STOP or free-timeout is sensed.

Bit4:

EXTHOLD: SMBus Setup and Hold Time Extension Enable.

 

This bit controls the SDA setup and hold times according to.

 

0: SDA Extended Setup and Hold Times disabled.

 

1: SDA Extended Setup and Hold Times enabled.

Bit3:

SMBTOE: SMBus SCL Timeout Detection Enable.

 

This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 3 to

 

reload while SCL is high and allows Timer 3 to count when SCL goes low. Timer 3 should be

 

programmed to generate interrupts at 25 ms, and the Timer 3 interrupt service routine

 

should reset SMBus communication.

Bit2:

SMBFTE: SMBus Free Timeout Detection Enable.

 

When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for

 

more than 10 SMBus clock source periods.

Bits1–0:

SMBCS1-SMBCS0: SMBus Clock Source Selection.

 

These two bits select the SMBus clock source, which is used to generate the SMBus bit

 

rate. The selected device should be configured according to Equation 17.1.

 

 

 

 

 

 

 

 

SMBCS1

 

SMBCS0

 

SMBus Clock Source

 

 

0

 

0

 

Timer 0 Overflow

 

 

0

 

1

 

Timer 1 Overflow

 

 

1

 

0

 

Timer 2 High Byte Overflow

 

 

1

 

1

 

Timer 2 Low Byte Overflow

 

200

Rev. 0.5

Page 200
Image 200
Silicon Laboratories C8051F347, C8051F346, C8051F341, C8051F343 SFR Definition 17.1. SMB0CF SMBus Clock/Configuration