C8051F340/1/2/3/4/5/6/7
SFR Definition 9.7. IE: Interrupt Enable
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | Reset Value |
EA
ESPI0
ET2
ES0
ET1
EX1
ET0
EX0
00000000
Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | SFR Address: |
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| (bit addressable) | 0xA8 |
Bit7: | EA: Enable All Interrupts. |
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| This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set- | |||||||
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| 0: Disable all interrupt sources. |
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| 1: Enable each interrupt according to its individual mask setting. |
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Bit6: | ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt. |
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| This bit sets the masking of the SPI0 interrupts. |
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| 0: Disable all SPI0 interrupts. |
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| 1: Enable interrupt requests generated by SPI0. |
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Bit5: | ET2: Enable Timer 2 Interrupt. |
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| This bit sets the masking of the Timer 2 interrupt. |
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| 0: Disable Timer 2 interrupt. |
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| 1: Enable interrupt requests generated by the TF2L or TF2H flags. |
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Bit4: | ES0: Enable UART0 Interrupt. |
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| This bit sets the masking of the UART0 interrupt. |
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| 0: Disable UART0 interrupt. |
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| 1: Enable UART0 interrupt. |
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Bit3: | ET1: Enable Timer 1 Interrupt. |
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| This bit sets the masking of the Timer 1 interrupt. |
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| 0: Disable all Timer 1 interrupt. |
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| 1: Enable interrupt requests generated by the TF1 flag. |
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Bit2: | EX1: Enable External Interrupt 1. |
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| This bit sets the masking of External Interrupt 1. |
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| 0: Disable external interrupt 1. |
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| 1: Enable interrupt requests generated by the /INT1 input. |
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Bit1: | ET0: Enable Timer 0 Interrupt. |
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| This bit sets the masking of the Timer 0 interrupt. |
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| 0: Disable all Timer 0 interrupt. |
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| 1: Enable interrupt requests generated by the TF0 flag. |
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Bit0: | EX0: Enable External Interrupt 0. |
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| This bit sets the masking of External Interrupt 0. |
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| 0: Disable external interrupt 0. |
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| 1: Enable interrupt requests generated by the /INT0 input. |
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90 | Rev. 0.5 |
