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Silicon Laboratories C8051F344, C8051F347, C8051F346, C8051F341, C8051F343, C8051F340 Reset Sources

Models: C8051F346 C8051F347 C8051F344 C8051F342 C8051F343 C8051F345 C8051F340 C8051F341

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Page 101

C8051F340/1/2/3/4/5/6/7

11. Reset Sources

Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:

•CIP-51 halts program execution

•Special Function Registers (SFRs) are initialized to their defined reset values

•External Port pins are forced to a known state

•Interrupts and timers are disabled.

All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data memory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered.

The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pull-ups are enabled dur- ing and after the reset. For VDD Monitor and Power-On Resets, the /RST pin is driven low until the device exits the reset state.

On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter- nal oscillator. Refer to Section “14. Oscillators” on page 135 for information on selecting and configuring the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source (Section “22.3. Watchdog Timer Mode” on page 272 details the use of the Watchdog Timer). Program execution begins at location 0x0000.

VDD

Px.x

Px.x

				Internal LF
				Oscillator

				Internal HF
				Oscillator


				Clock
				Multiplier


				External
XTAL1				External
XTAL1				Oscillator
XTAL2				Oscillator
				Drive
				Drive

Supply

Monitor

+Enable

-


	Power On
Comparator 0	Reset	'0'				/RST
	Reset	'0'				/RST
					(wired-OR)
					(wired-OR)

+
-	C0RSEF
	C0RSEF
Missing
Clock			Reset
Detector			Reset
(one-	PCA		Funnel
shot)	PCA	Software Reset (SWRSF)
EN	WDT	Software Reset (SWRSF)
	WDT

		Errant
	EN	FLASH	Enable
MCD Enable	WDT Enable	Operation
MCD Enable	WDT Enable
System		USB	VBUS
Clock	CIP-51	USB	VBUS
	CIP-51	Controller	Transition
Microcontroller		System Reset
	Core

Clock Select

Extended Interrupt

Handler

Figure 11.1. Reset Sources

Rev. 0.5

101

Image 101

Silicon Laboratories C8051F344, C8051F347, C8051F346, C8051F341, C8051F343, C8051F340, C8051F345, C8051F342 Reset Sources

Contents

HIGH-SPEED Controller Core Full Speed USB Flash MCU FamilyPrecision Internal Oscillators Rev Table Of Contents External Data Memory Interface and On-Chip Xram 117 Prefetch Engine Reset Sources 101Flash Memory 109 Port Input/Output 147 Oscillators 135Universal Serial Bus Controller USB0 163 SMBus 193UART0 211 Timers 243UART1 C8051F340/1/4/5 Only 219 Enhanced Serial Peripheral Interface SPI0 229Contact Information 282 Programmable Counter Array PCA0 26323. C2 Interface 279 C8051F340/1/2/3/4/5/6/7 Voltage Reference List of Figures and TablesAbsolute Maximum Ratings Flash Memory Prefetch Engine Reset SourcesExternal Data Memory Interface and On-Chip Xram OscillatorsUART0 SMBusUART1 C8051F340/1/4/5 Only Enhanced Serial Peripheral Interface SPI023.C2 Interface TimersProgrammable Counter Array PCA0 List of Registers C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 System Overview RAM Product Selection GuideTQFP48 LQFP32C8051F340/1/4/5 Block Diagram C8051F342/3/6/7 Block Diagram CIP-51 Microcontroller Core Additional FeaturesFully 8051 Compatible Improved ThroughputOn-Chip Clock and Reset On-Chip Memory Map for 64kB Devices C8051F340/2/4/6 On-Chip MemoryUniversal Serial Bus Controller USB Controller Block DiagramOn-Chip Debug Circuitry Voltage RegulatorProgrammable Digital I/O and Crossbar Digital Crossbar DiagramProgrammable Counter Array Serial PortsBit Analog to Digital Converter Bit ADC Block Diagram10. Comparator0 Block Diagram GND Absolute Maximum RatingsParameter Conditions Min Typ Max Units TBD Global DC Electrical CharacteristicsIndex to Electrical Characteristics Tables Table Title Name Pin Numbers Type Description 48-pin 32-pin Pinout and Package DefinitionsPin Definitions for the C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 C8051F340/1/4/5 Top View MIN TYP MAX Package DimensionsTQFP-48 GND VDD Regin Vbus LQFP-32 Pinout Diagram Top ViewLQFP-32 LQFP-32 Package DiagramC8051F340/1/2/3/4/5/6/7 Bit ADC ADC0 ADC0 Functional Block DiagramVref Analog MultiplexerTemperature Sensor Transfer Function Temperature SensorTemperature degrees C Starting a Conversion Modes of OperationTracking Modes Bit ADC Track and Conversion Example TimingSettling Time Requirements Differential Mode Single-Ended ModeEquation 5.1. ADC0 Settling Time Requirements AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 SFR Definition 5.1. AMX0P AMUX0 Positive Channel SelectAMX0P4-0 ADC0 Positive Input Pin Package ReservedAMX0N4-0 ADC0 Negative Input Pin Package SFR Definition 5.2. AMX0N AMUX0 Negative Channel SelectAMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 SFR Definition 5.4. ADC0H ADC0 Data Word MSB SFR Definition 5.3. ADC0CF ADC0 ConfigurationSFR Definition 5.5. ADC0L ADC0 Data Word LSB AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0LJSTAD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 SFR Definition 5.6. ADC0CN ADC0 ControlSFR Definition 5.8. ADC0GTL ADC0 Greater-Than Data Low Byte Programmable Window DetectorSFR Definition 5.10. ADC0LTL ADC0 Less-Than Data Low Byte SFR Definition 5.9. ADC0LTH ADC0 Less-Than Data High ByteADC Window Compare Example Right-Justified Single-Ended Data Window Detector In Single-Ended ModeADC Window Compare Example Right-Justified Differential Data Window Detector In Differential ModeAnalog Inputs ADC0 Electrical CharacteristicsConversion Rate Voltage Reference Voltage Reference Functional Block DiagramSFR Definition 6.1. REF0CN Reference Control Voltage Reference Electrical CharacteristicsRefsl Tempe Biase Refbe External Reference Refbe =Comparators Comparator Functional Block Diagram Comparator Hysteresis Plot CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 SFR Definition 7.1. CPT0CN Comparator0 ControlCMX0N1 CMX0N0 SFR Definition 7.2. CPT0MX Comparator0 MUX SelectionNegative Input Pin Package CMX0P1 CMX0P0CP0RIE CP0FIE CP0MD1 CP0MD0 SFR Definition 7.3. CPT0MD Comparator0 Mode SelectionMode CP0MD1 CP0MD0CP1EN CP1OUT CP1RIF CP1FIF SFR Definition 7.4. CPT1CN Comparator1 ControlCMX1N2 CMX1N1 CMX1N0 CMX1P2 CMX1P1 CMX1P0 SFR Definition 7.5. CPT1MX Comparator1 MUX SelectionCMX1N2 CMX1N1 CMX1N0 CMX1P2 CMX1P1 CMX1P0CP1RIE CP1FIE CP1MD1 CP1MD0 SFR Definition 7.6. CPT1MD Comparator1 Mode SelectionCP1MD1 CP1MD0 CP1 Response TimeComparator Electrical Characteristics Voltage Regulator Electrical Specifications Regulator Mode SelectionVoltage Regulator REG0 Vbus DetectionREG0 Configuration USB Bus-Powered REG0 Configuration USB Self-Powered, Regulator Disabled Regdis Vbstat Vbpol Regmod SFR Definition 8.1. REG0CN Voltage Regulator ControlCIP-51 Microcontroller CIP-51 Block DiagramPerformance Instruction SetInstruction and CPU Timing Logical Operations CIP-51 Instruction Set SummaryMovx Instruction and Program Memory Data Transfer Mnemonic Description Bytes Clock CyclesProgram Branching Boolean ManipulationC8051F340/1/2/3/4/5/6/7 Program Memory Memory OrganizationGeneral Purpose Registers Data MemoryBit Addressable Locations StackSpecial Function Registers Special Function Register SFR Memory MapADC0L Special Function RegistersRegister Address Description REF0CN PSWSPI0CN SFR Definition 9.2. DPH Data Pointer High Byte SFR Definition 9.1. DPL Data Pointer Low ByteSFR Definition 9.3. SP Stack Pointer Register DescriptionsSFR Definition 9.5. ACC Accumulator SFR Definition 9.4. PSW Program Status WordRS1 RS0 Register Bank AddressInterrupt Handler SFR Definition 9.6. B B RegisterMCU Interrupt Sources and Vectors External InterruptsInterrupt Latency Interrupt PrioritiesIT0 IN0PL IT1 IN1PLInterrupt Register Descriptions Interrupt SummaryESPI0 ET2 ES0 ET1 EX1 ET0 EX0 SFR Definition 9.7. IE Interrupt EnablePSPI0 PT2 PS0 PT1 PX1 PT0 PX0 SFR Definition 9.8. IP Interrupt PriorityET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 EUSB0 ESMB0 SFR Definition 9.9. EIE1 Extended Interrupt EnablePT3 PCP1 PCP0 PPCA0 PADC0 PWADC0 PUSB0 PSMB0 SFR Definition 9.10. EIP1 Extended Interrupt PrioritySFR Definition 9.12. EIP2 Extended Interrupt Priority SFR Definition 9.11. EIE2 Extended Interrupt EnableES1 Evbus PS1 PvbusIN1PL IN1SL2 IN1SL1 IN1SL0 IN0PL IN0SL2 IN0SL1 IN0SL0 SFR Definition 9.13. IT01CF INT0/INT1 ConfigurationIN1SL2-0 INT1 Port Pin IN0SL2-0 INT0 Port PinStop Mode Power Management ModesIdle Mode GF5 GF4 GF3 GF2 GF1 GF0 Stop Idle SFR Definition 9.14. Pcon Power ControlC8051F340/1/2/3/4/5/6/7 Pfen Flbwe Prefetch EngineSFR Definition 10.1. PFE0CN Prefetch Engine Control 100 Reset Sources Power-On and VDD Monitor Reset Timing Power-On ResetVdmen Power-Fail Reset / VDD MonitorSFR Definition 11.1. VDM0CN VDD Monitor Control Missing Clock Detector Reset External ResetComparator0 Reset PCA Watchdog Timer ResetUSB Reset Software ResetUsbrsf Ferror C0RSEF Swrsf Wdtrsf Mcdrsf Porsf Pinrsf SFR Definition 11.2. Rstsrc Reset SourceReset Electrical Characteristics 108 Flash Memory Flash Erase ProcedureProgramming The Flash Memory Flash Lock and Key FunctionsFlash Write Procedure Security Options Flash Electrical CharacteristicsNon-volatile Data Storage Flash Program Memory Map and Security Byte Accessing Flash from the C2 debug interface Pswe SFR Definition 12.1. Psctl Program Store R/W ControlSFR Definition 12.2. Flkey Flash Lock and Key Flrt SFR Definition 12.3. Flscl Flash ScaleFose 116 Bit Movx Example Accessing XramExternal Data Memory Interface and On-Chip Xram USB Fifo Space Accessing USB Fifo SpacePort Configuration Configuring the External Memory InterfacePGSEL7 PGSEL6 PGSEL5 PGSEL4 PGSEL3 PGSEL2 PGSEL1 PGSEL0 Usbfae EMD2 EMD1 EMD0 EALE1 EALE0 SFR Definition 13.2. EMI0CF External Memory ConfigurationMultiplexed and Non-multiplexed Selection Multiplexed ConfigurationNon-multiplexed Configuration Non-multiplexed Configuration Example Memory Mode SelectionInternal Xram Only Split Mode without Bank SelectExternal Only Split Mode with Bank SelectTiming EAS1 EAS0 ERW3 EWR2 EWR1 EWR0 EAH1 EAH0 SFR Definition 13.3. EMI0TC External Memory Timing ControlBit Movx EMI0CF42 = ‘101’, ‘110’, or ‘111’ Non-multiplexed ModeEmif Write Data Emif Read DataBit Movx without Bank Select EMI0CF42 = ‘101’ or ‘111’ Non-multiplexed 8-bit Movx without Bank Select TimingBit Movx with Bank Select EMI0CF42 = ‘110’ Non-multiplexed 8-bit Movx with Bank Select TimingBit Movx EMI0CF42 = ‘001’, ‘010’, or ‘011’ Multiplexed ModeBit Movx without Bank Select EMI0CF42 = ‘001’ or ‘011’ Multiplexed 8-bit Movx without Bank Select TimingBit Movx with Bank Select EMI0CF42 = ‘010’ 10. Multiplexed 8-bit Movx with Bank Select TimingParameter Description Min Max Units AC Parameters for External Memory Interface134 Oscillators Oscillator DiagramProgrammable Internal High-Frequency H-F Oscillator Internal H-F Oscillator Suspend ModeSFR Definition 14.1. Oscicn Internal H-F Oscillator Control Ioscen Ifrdy Suspend IFCN1 IFCN0Osccal Programmable Internal Low-Frequency L-F OscillatorCalibrating the Internal L-F Oscillator Osclen Osclrdy OSCLF3 OSCLF2 OSCLF1 OSCLF0 OSCLD1 OSCLD0 SFR Definition 14.3. Osclcn Internal L-F Oscillator ControlExternal Crystal Example Clocking Timers Directly Through the External OscillatorExternal Oscillator Drive Circuit External Capacitor Example External RC ExampleXfcn SFR Definition 14.4. Oscxcn External Oscillator ControlXtlvld XOSCMD2 XOSCMD1 XOSCMD0 XFCN2 XFCN1 XFCN0 SFR Definition 14.5. Clkmul Clock Multiplier Control Clock MultiplierMulen Mulinit Mulrdy Mulsel MulselInternal Oscillator Clock Signal External Oscillator Clock SignalSystem and USB Clock Selection System Clock SelectionUsbclk Clksl SFR Definition 14.6. Clksel Clock SelectUsbclk ClkslExternal USB Clock Requirements Oscillator Electrical Characteristics146 Port Input/Output Port I/O Functional Block Diagram Port 0 through PortPort I/O Cell Block Diagram Priority Crossbar Decoder Crossbar Priority Decoder with No Pins SkippedCrossbar Priority Decoder with Crystal Pins Skipped Port I/O Initialization CP1AE CP1E CP0AE CP0E Syscke SMB0E SPI0E URT0E SFR Definition 15.1. XBR0 Port I/O Crossbar RegisterSFR Definition 15.3. XBR2 Port I/O Crossbar Register SFR Definition 15.2. XBR1 Port I/O Crossbar RegisterWeakpud Xbare T1E T0E Ecie PCA0ME URT1ESFR Definition 15.4. P0 Port0 Latch SFR Definition 15.5. P0MDIN Port0 Input ModeGeneral Purpose Port I/O SFR Definition 15.7. P0SKIP Port0 Skip SFR Definition 15.6. P0MDOUT Port0 Output ModeSFR Definition 15.8. P1 Port1 Latch SFR Definition 15.9. P1MDIN Port1 Input ModeSFR Definition 15.10. P1MDOUT Port1 Output Mode SFR Definition 15.12. P2 Port2 Latch SFR Definition 15.13. P2MDIN Port2 Input ModeSFR Definition 15.11. P1SKIP Port1 Skip SFR Definition 15.15. P2SKIP Port2 Skip SFR Definition 15.14. P2MDOUT Port2 Output ModeSFR Definition 15.16. P3 Port3 Latch SFR Definition 15.17. P3MDIN Port3 Input ModeSFR Definition 15.18. P3MDOUT Port3 Output Mode SFR Definition 15.20. P4 Port4 Latch SFR Definition 15.19. P3SKIP Port3 SkipSFR Definition 15.22. P4MDOUT Port4 Output Mode SFR Definition 15.21. P4MDIN Port4 Input ModePort I/O DC Electrical Characteristics Universal Serial Bus Controller USB0 USB0 Block DiagramEndpoint Addressing Scheme Endpoint AddressingUSB Transceiver Endpoint Associated Pipes USB Protocol AddressPHYTST10 SFR Definition 16.1. USB0XCN USB0 Transceiver ControlPren Phyen Speed PHYTST1 PHYTST0 Dfrec USB0 Register Access Scheme USB Register AccessBusy Autord Usbaddr SFR Definition 16.2. USB0ADR USB0 Indirect AddressSFR Definition 16.3. USB0DAT USB0 Data Index USB0 Controller RegistersUSB Register Definition 16.4. Index USB0 Endpoint Index USB Register Definition 16.5. Clkrec Clock Recovery Control USB Clock ConfigurationCommunication Speed USB Clock 4x Clock Multiplier Input CRE Crssen CrlowFifo Management Fifo Split ModeFifo Access Fifo ConfigurationsFifo Double Buffering FifodataUSB Register Definition 16.7. Faddr USB0 Function Address Function Configuration and ControlFunction Addressing 174 Isoud Usbinh Usbrst Resume Susmd Susen USB Register Definition 16.8. Power USB0 PowerInterrupts USB Register Definition 16.9. Framel USB0 Frame Number LowOUT3 OUT2 OUT1 IN3 IN2 IN1 EP0SOF Rstint Rsuint Susint USB Register Definition 16.13. Cmint USB0 Common InterruptOUT3E OUT2E OUT1E IN3E IN2E IN1E EP0ESofe Rstinte Rsuinte Susinte Serial Interface EngineEndpoint0 Endpoint0 in Transactions Endpoint0 Setup TransactionsEndpoint0 OUT Transactions Ssuend USB Register Definition 16.17. E0CSR USB0 Endpoint0 ControlSsuend Soprdy Sdstl Suend Dataend Ststl Inprdy Oprdy Controlling Endpoints1-3 Configuring Endpoints1-3Endpoints1-3 in Interrupt or Bulk Mode Endpoints1-3 in Isochronous Mode A packet being transmitted Clrdt Ststl Sdstl Flush Undrun Fifone InprdyDbien ISO Dirsel Fcdt Split Endpoints1-3 OUT Interrupt or Bulk ModeControlling Endpoints1-3 OUT Endpoints1-3 OUT Isochronous Mode Clrdt Ststl Sdstl Flush Daterr Ovrun Fifoful Oprdy E0CH Dboen ISOEocl Receiver USB Transceiver Electrical Characteristics192 SMBus SMBus Block DiagramSupporting Documents SMBus ConfigurationArbitration SMBus TransactionSCL Low Timeout Using the SMBusSCL High SMBus Free Timeout Clock Low ExtensionTion Register on SMBus Clock Source Selection SMBus Configuration RegisterEquation 17.1. Minimum SCL High and Low Times Equation 17.2. Typical SMBus Bit RateExthold Minimum SDA Setup and Hold TimesMinimum SDA Setup Time Minimum SDA Hold Time Ensmb INH Busy Exthold Smbtoe Smbfte SMBCS1 SMBCS0 SFR Definition 17.1. SMB0CF SMBus Clock/ConfigurationSMB0CN Control Register Master Txmode STA STO Ackrq Arblost ACK SFR Definition 17.2. SMB0CN SMBus ControlSources for Hardware Changes to SMB0CN Bit Set by Hardware When Cleared by Hardware WhenSFR Definition 17.3. SMB0DAT SMBus Data Master Transmitter ModeSMBus Transfer Modes Data RegisterTypical Master Transmitter Sequence Typical Master Receiver Sequence Master Receiver ModeTypical Slave Receiver Sequence Slave Receiver ModeTypical Slave Transmitter Sequence SMBus Status Decoding Slave Transmitter ModeStart Values ReadCurrent SMbus State Typical Response Options Slave byte was transmitted No action required expect UART0 UART0 Block DiagramOperational Modes Enhanced Baud Rate GenerationEquation 18.1. UART0 Baud Rate Bit Uart Uart Interconnect DiagramBit Uart Timing Diagram Multiprocessor Communications Master Slave Device TI0 RI0 SFR Definition 18.1. SCON0 Serial Port 0 ControlS0MODE MCE0 REN0 SFR Definition 18.2. SBUF0 Serial UART0 Port Data Buffer T1M Timer Baud Rate Error Divide Source Pre-scale Target Actual Baud Oscillator Timer ClockSCA1-SCA0 Rate bps Factor SelectUART1 C8051F340/1/4/5 Only UART1 Block DiagramBaud Rate Generator Baud Rate Generator Settings for Standard Baud RatesEquation 19.1. UART1 Baud Rate SBRLH1SBRLL1UART1 Timing Without Parity or Extra Bit Data FormatData Reception Configuration and OperationData Transmission Multiprocessor Communications Fifo SFR Definition 19.1. SCON1 UART1 ControlOVR1 PERR1 THRE1 REN1 TBX1 RBX1 TI1 RI1 MCE1 S1PT1 S1PT0 PE1 S1DL1 S1DL0 XBE1 SBL1 SFR Definition 19.2. SMOD1 UART1 ModeSB1PS1 SB1PS0 SFR Definition 19.3. SBUF1 UART1 Data BufferSB1RUN Rev 227 228 Enhanced Serial Peripheral Interface SPI0 SPI Block DiagramMaster Out, Slave In Mosi Signal DescriptionsMaster In, Slave Out Miso Serial Clock SCKSPI0 Master Mode Operation Multiple-Master Mode Connection Diagram SPI0 Interrupt Sources SPI0 Slave Mode OperationSerial Clock Timing Master Mode Data/Clock TimingSlave Mode Data/Clock Timing Ckpha = Spibsy Msten Ckpha Ckpol Slvsel Nssin Srmt Rxbmt SFR Definition 20.1. SPI0CFG SPI0 ConfigurationSPI Special Function Registers Spif Wcol Modf Rxovrn NSSMD1 NSSMD0 Txbmt Spien SFR Definition 20.2. SPI0CN SPI0 ControlSCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SFR Definition 20.3. SPI0CKR SPI0 Clock RateSFR Definition 20.4. SPI0DAT SPI0 Data SPI Master Timing Ckpha = 10. SPI Slave Timing Ckpha = Only Slave Mode Timing* See FigureSPI Slave Timing Parameters 242 Timer 0 and Timer TimersMode 0 13-bit Counter/Timer Timer 0 and Timer 1 Modes Timer 2 Modes Timer 3 ModesTR0 GATE0 INT0 Mode 1 16-bit Counter/TimerCounter/Timer Mode 2 8-bit Counter/Timer with Auto-Reload T0 Mode 2 Block DiagramMode 3 Two 8-bit Counter/Timers Timer 0 Only T0 Mode 3 Block DiagramTF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SFR Definition 21.1. Tcon Timer ControlGATE1 SFR Definition 21.2. Tmod Timer ModeGATE0 T1M1 T1M0T3MH T3ML T2MH T2ML T1M T0M SCA1 SCA0 SFR Definition 21.3. Ckcon Clock ControlSCA1 SCA0 Prescaled ClockSFR Definition 21.5. TL1 Timer 1 Low Byte SFR Definition 21.4. TL0 Timer 0 Low ByteSFR Definition 21.6. TH0 Timer 0 High Byte SFR Definition 21.7. TH1 Timer 1 High ByteBit Timer with Auto-Reload TimerT2MH T2XCLK Bit Timers with Auto-ReloadTMR2H Clock Source T2ML T2XCLKTimer 2 Capture Mode T2SPLIT = ‘0’ Timer 2 Capture Mode T2SPLIT = ‘1’ TF2H TF2L TF2LEN T2CE T2SPLIT TR2 T2CSS T2XCLK SFR Definition 21.8. TMR2CN Timer 2 ControlSFR Definition 21.12. TMR2H Timer 2 High Byte SFR Definition 21.11. TMR2L Timer 2 Low ByteTimer 3 16-Bit Mode Block Diagram TMR3H Clock Source T3MH T3XCLKT3ML T3XCLK TMR3L Clock SourceUSB Start-of-Frame Capture 10. Timer 3 Capture Mode T3SPLIT = ‘0’11. Timer 3 Capture Mode T3SPLIT = ‘1’ TF3H TF3L TF3LEN T3CE T3SPLIT TR3 T3CSS T3XCLK SFR Definition 21.13. TMR3CN Timer 3 ControlSFR Definition 21.17. TMR3H Timer 3 High Byte SFR Definition 21.16. TMR3L Timer 3 Low ByteProgrammable Counter Array PCA0 PCA Timebase Input Options PCA Counter/TimerCPS2 CPS1 CPS0 TimebaseOperation Mode PCA0CPM Register Settings for PCA Capture/Compare ModulesCapture/Compare Modules PWM16 Ecom Capp Capn MAT TOG EccfEdge-triggered Capture Mode PCA Capture Mode DiagramSoftware Timer Compare Mode PCA Software Timer Mode DiagramHigh Speed Output Mode PCA High Speed Output Mode DiagramEquation 22.1. Square Wave Frequency Output Frequency Output ModeEquation 22.2 -Bit PWM Duty Cycle Bit Pulse Width Modulator ModeEquation 22.3 -Bit PWM Duty Cycle PCA 16-Bit PWM ModeWatchdog Timer Operation Watchdog Timer ModeWatchdog Timer Timeout Intervals1 Equation 22.4. Watchdog Timer Offset in PCA ClocksWatchdog Timer Usage PCA0CPL4CCF4 CCF3 CCF2 CCF1 CCF0 Register Descriptions for PCASFR Definition 22.1. PCA0CN PCA Control Cidl Wdte Wdlck CPS2 CPS1 CPS0 ECF SFR Definition 22.2. PCA0MD PCA ModeSFR Definition 22.3. PCA0CPMn PCA Capture/Compare Mode SFR Definition 22.6. PCA0CPLn PCA Capture Module Low Byte SFR Definition 22.4. PCA0L PCA Counter/Timer Low ByteSFR Definition 22.5. PCA0H PCA Counter/Timer High Byte SFR Definition 22.7. PCA0CPHn PCA Capture Module High Byte 23.1. C2 Interface Registers 23. C2 InterfaceC2 Register Definition 23.1. C2ADD C2 Address C2 Register Definition 23.2. Deviceid C2 Device IDC2 Register Definition 23.3. Revid C2 Revision ID Code CommandTypical C2 Pin Sharing 23.2. C2 Pin SharingContact Information