Silicon Laboratories C8051F346, C8051F347, C8051F341, C8051F343 IN3 IN2 IN1 EP0, OUT3 OUT2 OUT1

C8051F340/1/2/3/4/5/6/7

USB Register Definition 16.11. IN1INT: USB0 IN Endpoint Interrupt

R		R	R	R	R	R	R	R	Reset Value
-		-	-	-	IN3	IN2	IN1	EP0	00000000
Bit7		Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0	USB Address:
									0x02
Bits7–4:	Unused. Read = 0000b. Write = don’t care.
Bit3:	IN3: IN Endpoint 3 Interrupt-pending Flag
	This bit is cleared when software reads the IN1INT register.
	0: IN Endpoint 3 interrupt inactive.
	1: IN Endpoint 3 interrupt active.
Bit2:	IN2: IN Endpoint 2 Interrupt-pending Flag
	This bit is cleared when software reads the IN1INT register.
	0: IN Endpoint 2 interrupt inactive.
	1: IN Endpoint 2 interrupt active.
Bit1:	IN1: IN Endpoint 1 Interrupt-pending Flag
	This bit is cleared when software reads the IN1INT register.
	0: IN Endpoint 1 interrupt inactive.
	1: IN Endpoint 1 interrupt active.
Bit0:	EP0: Endpoint 0 Interrupt-pending Flag
	This bit is cleared when software reads the IN1INT register.
	0: Endpoint 0 interrupt inactive.
	1: Endpoint 0 interrupt active.

USB Register Definition 16.12. OUT1INT: USB0 Out Endpoint Interrupt

R		R	R	R	R	R	R	R	Reset Value
-		-	-	-	OUT3	OUT2	OUT1	-	00000000
Bit7		Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0	USB Address:
									0x04
Bits7–4:	Unused. Read = 0000b. Write = don’t care.
Bit3:	OUT3: OUT Endpoint 3 Interrupt-pending Flag
	This bit is cleared when software reads the OUT1INT register.
	0: OUT Endpoint 3 interrupt inactive.
	1: OUT Endpoint 3 interrupt active.
Bit2:	OUT2: OUT Endpoint 2 Interrupt-pending Flag
	This bit is cleared when software reads the OUT1INT register.
	0: OUT Endpoint 2 interrupt inactive.
	1: OUT Endpoint 2 interrupt active.
Bit1:	OUT1: OUT Endpoint 1 Interrupt-pending Flag
	This bit is cleared when software reads the OUT1INT register.
	0: OUT Endpoint 1 interrupt inactive.
	1: OUT Endpoint 1 interrupt active.
Bit0:	Unused. Read = 0; Write = don’t care.

Rev. 0.5 177