Silicon Laboratories C8051F342, C8051F347, C8051F346 Power-Fail Reset / VDD Monitor, Vdmen

C8051F340/1/2/3/4/5/6/7

11.2. Power-Fail Reset / VDD Monitor

When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor will drive the /RST pin low and hold the CIP-51 in a reset state (see Figure 11.2). When VDD returns to a level above VRST, the CIP-51 will be released from the reset state. Note that even though inter- nal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The VDD monitor is enabled after power-on resets; however its defined state (enabled/disabled) is not altered by any other reset source. For example, if the VDD monitor is enabled and a software reset is performed, the VDD monitor will still be enabled after the reset.

Important Note: The VDD monitor must be enabled before it is selected as a reset source. Selecting the VDD monitor as a reset source before it is enabled and stabilized will cause a system reset. The procedure for configuring the VDD monitor as a reset source is shown below:

Step 1. Enable the VDD monitor (VDM0CN.7 = ‘1’).

Step 2. Wait for the VDD monitor to stabilize (see Table 11.1 for the VDD Monitor turn-on time). Step 3. Select the VDD monitor as a reset source (RSTSRC.1 = ‘1’).

See Figure 11.2 for VDD monitor timing. See Table 11.1 for complete electrical characteristics of the VDD monitor.

SFR Definition 11.1. VDM0CN: VDD Monitor Control

R/W R R R R R R R Reset Value

VDMEN

VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved

Variable

Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0	SFR Address:
								0xFF
Bit7:	VDMEN: VDD Monitor Enable.
	This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system resets
	until it is also selected as a reset source in register RSTSRC (SFR Definition 11.2). The VDD
	Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the
	VDD monitor as a reset source before it has stabilized will generate a system reset.
	See Table 11.1 for the minimum VDD Monitor turn-on time. The VDD Monitor is enabled fol-
	lowing all POR resets.
	0: VDD Monitor Disabled.
	1: VDD Monitor Enabled.
Bit6:	VDDSTAT: VDD Status.
	This bit indicates the current power supply status (VDD Monitor output).

0:VDD is at or below the VDD monitor threshold.

1:VDD is above the VDD monitor threshold. Bits5–0: Reserved. Read = Variable. Write = don’t care.

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