Silicon Laboratories C8051F341 T3MH T3XCLK, TMR3H Clock Source, T3ML T3XCLK, TMR3L Clock Source

C8051F340/1/2/3/4/5/6/7

21.3.2. 8-bit Timers with Auto-Reload

When T3SPLIT is ‘1’ and T3CE = ‘0’, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers operate in auto-reload mode as shown in Figure 21.5. TMR3RLL holds the reload value for TMR3L; TMR3RLH holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is always running when configured for 8-bit Mode.

Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or the clock defined by the Timer 3 External Clock Select bit (T3XCLK in TMR3CN), as follows:

T3MH	T3XCLK	TMR3H Clock Source
0	0	SYSCLK / 12
0	1	External Clock / 8
1	X	SYSCLK

T3ML	T3XCLK	TMR3L Clock Source
0	0	SYSCLK / 12
0	1	External Clock / 8
1	X	SYSCLK

The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over- flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not cleared by hardware and must be manually cleared by software.

	T3XCLK
SYSCLK / 12
	0
	0
External Clock / 8	1
		1

SYSCLK

1

CKCON

T T T T T T S S 3 3 2 2 1 0 C C M M M M M M A A

H L H L 1 0

TCLK

TR3

TMR3RLH Reload

TMR3H

TMR3RLL Reload

To ADC

	TF3H
	TF3L
TMR3CN	TF3LEN
	T3CE
	T3SPLIT
	TR3
	T3CSS
	T3XCLK

Interrupt

TCLK TMR3L

0

Figure 21.9. Timer 3 8-Bit Mode Block Diagram

258 Rev. 0.5