Silicon Laboratories C8051F343, C8051F347, C8051F346, C8051F341, C8051F340 Port Input/Output

C8051F340/1/2/3/4/5/6/7

15. Port Input/Output

Digital and analog resources are available through 40 I/O pins (C8051F340/1/4/5) or 25 I/O pins (C8051F342/3/6/7). Port pins are organized as shown in Figure 15.1. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input; Port pins P0.0-P3.7 can be assigned to one of the internal digital resources as shown in Figure 15.3. The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regardless of the Crossbar settings.

The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder (Figure 15.3 and Figure 15.4). The registers XBR0, XBR1, and XBR2 defined in SFR Definition 15.1, SFR Definition 15.2, and SFR Definition 15.3, are used to select internal digital functions.

All Port I/Os are 5 V tolerant (refer to Figure 15.2 for the Port cell circuit). The Port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3,4). Com- plete Electrical Specifications for Port I/O are given in Table 15.1 on page 162.

XBR0, XBR1, XBR2,	PnMDOUT,
PnSKIP Registers	PnMDIN Registers

Highest Priority

(Internal Digital Signals)

Lowest Priority

(Port Latches)

2

UART0

4

SPI

2

SMBus

CP0	2
Outputs	2
CP1
Outputs
SYSCLK
		6
PCA
	2
T0, T1
	2
UART1*

8

P0	(P0.0-P0.7)
	8
P1	(P1.0-P1.7)
	8
P2	(P2.0-P2.7)
	8
P3	(P3.0-P3.7*)

Priority

Decoder

Digital

Crossbar

8	P0	P0.0
	I/O
	Cells	P0.7
8	P1	P1.0
	I/O
	Cells	P1.7
8	P2	P2.0
	I/O
	Cells	P2.7
8	P3	P3.0
	I/O
	Cells	P3.7*

*Note: P3.1-P3.7 and UART1 only available on 48-pin package

Figure 15.1. Port I/O Functional Block Diagram (Port 0 through Port 3)

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