C8051F340/1/2/3/4/5/6/7
SFR Definition 21.9. TMR2RLL: Timer 2 Reload Register Low Byte
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | Reset Value |
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| 00000000 |
Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | SFR Address: |
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| 0xCA |
Bits
TMR2RLL holds the low byte of the reload value for Timer 2 when operating in
SFR Definition 21.10. TMR2RLH: Timer 2 Reload Register High Byte
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | Reset Value |
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| 00000000 |
Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | SFR Address: |
0xCB
Bits
The TMR2RLH holds the high byte of the reload value for Timer 2 when operating in
SFR Definition 21.11. TMR2L: Timer 2 Low Byte
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | Reset Value |
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| 00000000 |
Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | SFR Address: |
0xCC
Bits
In
SFR Definition 21.12. TMR2H Timer 2 High Byte
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | Reset Value |
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| 00000000 |
Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | SFR Address: |
0xCD
Bits
In
256 | Rev. 0.5 |