Silicon Laboratories C8051F345 SFR Definition 9.11. EIE2 Extended Interrupt Enable, ES1 Evbus

C8051F340/1/2/3/4/5/6/7

SFR Definition 9.11. EIE2: Extended Interrupt Enable 2

R/W		R/W	R/W	R/W	R/W	R/W	R/W	R/W	Reset Value
-		-	-	-	-	-	ES1	EVBUS	00000000
Bit7		Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0	SFR Address:
									0xE7
Bits7–2:	UNUSED. Read = 000000b. Write = don’t care.
Bit1:	ES1: Enable UART1 Interrupt.
	This bit sets the masking of the UART1 interrupt.
	0: Disable UART1 interrupt.
	1: Enable UART1 interrupt.
Bit0:	EVBUS: Enable VBUS Level Interrupt.
	This bit sets the masking of the VBUS interrupt.

0: Disable all VBUS interrupts.

1: Enable interrupt requests generated by VBUS level sense.

SFR Definition 9.12. EIP2: Extended Interrupt Priority 2

R/W		R/W	R/W	R/W	R/W	R/W	R/W	R/W	Reset Value
-		-	-	-	-	-	PS1	PVBUS	00000000
Bit7		Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0	SFR Address:
									0xF7
Bits7–2:	UNUSED. Read = 000000b. Write = don’t care.
Bit1:	PS1: UART1 Interrupt Priority Control.
	This bit sets the priority of the UART1 interrupt.
	0: UART1 interrupt set to low priority level.
	1: UART1 interrupts set to high priority level.
Bit0:	PVBUS: VBUS Level Interrupt Priority Control.
	This bit sets the priority of the VBUS interrupt.
	0: VBUS interrupt set to low priority level.
	1: VBUS interrupt set to high priority level.

94 Rev. 0.5