C8051F340/1/2/3/4/5/6/7
5.4.Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 conversion results to
The Window Detector registers must be written with the same format (left/right justified, signed/unsigned) as that of the current ADC configuration (left/right justified,
SFR Definition 5.7. ADC0GTH: ADC0
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | Reset Value |
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| 11111111 |
Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | SFR Address: |
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| 0xC4 |
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset Value |
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| 11111111 | |
Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
| SFR Address: |
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| 0xC3 |
52 | Rev. 0.5 |