Silicon Laboratories C8051F345 Equation 22.2 -Bit PWM Duty Cycle, Bit Pulse Width Modulator Mode

C8051F340/1/2/3/4/5/6/7

22.2.5. 8-Bit Pulse Width Modulator Mode

Each module can be used independently to generate a pulse width modulated (PWM) output on its associ- ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the CEXn output will be reset (see Figure 22.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn register enables 8-Bit Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given by Equation 22.2.

Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/ Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.

(256 – PCA0CPHn)

DutyCycle = ---------------------------------------------------

256

Equation 22.2. 8-Bit PWM Duty Cycle

Using Equation 22.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is 0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.

Write to

PCA0CPLn0

ENB

Reset

Write to

PCA0CPHn ENB

1

PCA0CPMn

P E C C M T P E W C A A A O W C M O P P T G M C 1 M P N n n n F

6 n n n n n

0 0 0 x 0 x

Enable

PCA Timebase

PCA0CPHn

PCA0CPLn

8-bit

Comparator

PCA0L

match S SET Q

R CLR Q

Overflow

CEXn

Crossbar Port I/O

Figure 22.8. PCA 8-Bit PWM Mode Diagram

270 Rev. 0.5