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Silicon Laboratories C8051F343, C8051F347 UART1 C8051F340/1/4/5 Only, UART1 Block Diagram

Models: C8051F346 C8051F347 C8051F344 C8051F342 C8051F343 C8051F345 C8051F340 C8051F341

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C8051F340/1/2/3/4/5/6/7

19. UART1 (C8051F340/1/4/5 Only)

UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates (details in Section “19.1. Baud Rate Generator” on page 220). A received data FIFO allows UART1 to receive up to three data bytes before data is lost and an overflow occurs.

UART1 has six associated SFRs. Three are used for the Baud Rate Generator (SBCON1, SBRLH1, and SBRLL1), two are used for data formatting, control, and status functions (SCON1, SMOD1), and one is used to send and receive data (SBUF1). The single SBUF1 location provides access to both the transmit holding register and the receive FIFO. Writes to SBUF1 always access the Transmit Holding Register.

Reads of SBUF1 always access the first byte of the Receive FIFO; it is not possible to read data from the Transmit Holding Register.

With UART1 interrupts enabled, an interrupt is generated each time a transmit is completed (TI1 is set in SCON1), or a data byte has been received (RI1 is set in SCON1). The UART1 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART1 interrupt (transmit complete or receive complete). Note that if additional bytes are available in the Receive FIFO, the RI1 bit cannot be cleared by software.

		Baud Rate Generator
	SBRLH1	SBRLL1	Overflow
			Overflow
SYSCLK	Timer (16-bit)		Pre-Scaler
	Timer (16-bit)		(1, 4, 12, 48)
		EN	(1, 4, 12, 48)
		SB1RUN	SB1PS1 SB1PS0
			SBCON1

Data Formatting

SMOD1

MCE1S1PT1S1PT0PE1S1DL1S1DL0XBE1SBL1

Control / Status
	SCON1
OVR1 PERR1	THRE1 REN1 TBX1 RBX1	TI1	RI1

UART1

Interrupt

	TX	TX1
	Logic	TX1
	Logic

TX Holding

Register

Write to SBUF1 SBUF1

Read of SBUF1

RX FIFO (3 Deep)


RX				RX1
Logic				RX1
Logic

Figure 19.1. UART1 Block Diagram

Rev. 0.5

219

Image 219

Silicon Laboratories C8051F343, C8051F347, C8051F346, C8051F341, C8051F344 UART1 C8051F340/1/4/5 Only, UART1 Block Diagram

Contents

Full Speed USB Flash MCU Family Precision Internal OscillatorsHIGH-SPEED Controller Core Rev Table Of Contents Prefetch Engine Reset Sources 101 Flash Memory 109External Data Memory Interface and On-Chip Xram 117 SMBus 193 Oscillators 135Port Input/Output 147 Universal Serial Bus Controller USB0 163Enhanced Serial Peripheral Interface SPI0 229 Timers 243UART0 211 UART1 C8051F340/1/4/5 Only 219Programmable Counter Array PCA0 263 23. C2 Interface 279Contact Information 282 C8051F340/1/2/3/4/5/6/7 List of Figures and Tables Absolute Maximum RatingsVoltage Reference Oscillators Prefetch Engine Reset SourcesFlash Memory External Data Memory Interface and On-Chip XramEnhanced Serial Peripheral Interface SPI0 SMBusUART0 UART1 C8051F340/1/4/5 OnlyTimers Programmable Counter Array PCA023.C2 Interface List of Registers C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 System Overview LQFP32 Product Selection GuideRAM TQFP48C8051F340/1/4/5 Block Diagram C8051F342/3/6/7 Block Diagram Improved Throughput Additional FeaturesCIP-51 Microcontroller Core Fully 8051 CompatibleOn-Chip Clock and Reset On-Chip Memory Map for 64kB Devices C8051F340/2/4/6 On-Chip MemoryUniversal Serial Bus Controller USB Controller Block DiagramOn-Chip Debug Circuitry Voltage RegulatorProgrammable Digital I/O and Crossbar Digital Crossbar DiagramProgrammable Counter Array Serial PortsBit Analog to Digital Converter Bit ADC Block Diagram10. Comparator0 Block Diagram Absolute Maximum Ratings Parameter Conditions Min Typ Max UnitsGND TBD Global DC Electrical CharacteristicsIndex to Electrical Characteristics Tables Table Title Pinout and Package Definitions Pin Definitions for the C8051F340/1/2/3/4/5/6/7Name Pin Numbers Type Description 48-pin 32-pin C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 C8051F340/1/4/5 Top View Package Dimensions TQFP-48MIN TYP MAX GND VDD Regin Vbus LQFP-32 Pinout Diagram Top ViewLQFP-32 LQFP-32 Package DiagramC8051F340/1/2/3/4/5/6/7 Bit ADC ADC0 ADC0 Functional Block DiagramVref Analog MultiplexerTemperature Sensor Transfer Function Temperature SensorTemperature degrees C Starting a Conversion Modes of OperationTracking Modes Bit ADC Track and Conversion Example TimingDifferential Mode Single-Ended Mode Equation 5.1. ADC0 Settling Time RequirementsSettling Time Requirements Reserved SFR Definition 5.1. AMX0P AMUX0 Positive Channel SelectAMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 AMX0P4-0 ADC0 Positive Input Pin PackageSFR Definition 5.2. AMX0N AMUX0 Negative Channel Select AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0AMX0N4-0 ADC0 Negative Input Pin Package AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0LJST SFR Definition 5.3. ADC0CF ADC0 ConfigurationSFR Definition 5.4. ADC0H ADC0 Data Word MSB SFR Definition 5.5. ADC0L ADC0 Data Word LSBAD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 SFR Definition 5.6. ADC0CN ADC0 ControlSFR Definition 5.8. ADC0GTL ADC0 Greater-Than Data Low Byte Programmable Window DetectorSFR Definition 5.10. ADC0LTL ADC0 Less-Than Data Low Byte SFR Definition 5.9. ADC0LTH ADC0 Less-Than Data High ByteADC Window Compare Example Right-Justified Single-Ended Data Window Detector In Single-Ended ModeADC Window Compare Example Right-Justified Differential Data Window Detector In Differential ModeADC0 Electrical Characteristics Conversion RateAnalog Inputs Voltage Reference Voltage Reference Functional Block DiagramExternal Reference Refbe = Voltage Reference Electrical CharacteristicsSFR Definition 6.1. REF0CN Reference Control Refsl Tempe Biase RefbeComparators Comparator Functional Block Diagram Comparator Hysteresis Plot CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 SFR Definition 7.1. CPT0CN Comparator0 ControlCMX0P1 CMX0P0 SFR Definition 7.2. CPT0MX Comparator0 MUX SelectionCMX0N1 CMX0N0 Negative Input Pin PackageCP0MD1 CP0MD0 SFR Definition 7.3. CPT0MD Comparator0 Mode SelectionCP0RIE CP0FIE CP0MD1 CP0MD0 ModeCP1EN CP1OUT CP1RIF CP1FIF SFR Definition 7.4. CPT1CN Comparator1 ControlCMX1P2 CMX1P1 CMX1P0 SFR Definition 7.5. CPT1MX Comparator1 MUX SelectionCMX1N2 CMX1N1 CMX1N0 CMX1P2 CMX1P1 CMX1P0 CMX1N2 CMX1N1 CMX1N0CP1 Response Time SFR Definition 7.6. CPT1MD Comparator1 Mode SelectionCP1RIE CP1FIE CP1MD1 CP1MD0 CP1MD1 CP1MD0Comparator Electrical Characteristics Vbus Detection Regulator Mode SelectionVoltage Regulator Electrical Specifications Voltage Regulator REG0REG0 Configuration USB Bus-Powered REG0 Configuration USB Self-Powered, Regulator Disabled Regdis Vbstat Vbpol Regmod SFR Definition 8.1. REG0CN Voltage Regulator ControlCIP-51 Microcontroller CIP-51 Block DiagramInstruction Set Instruction and CPU TimingPerformance CIP-51 Instruction Set Summary Movx Instruction and Program MemoryLogical Operations Data Transfer Mnemonic Description Bytes Clock CyclesProgram Branching Boolean ManipulationC8051F340/1/2/3/4/5/6/7 Program Memory Memory OrganizationStack Data MemoryGeneral Purpose Registers Bit Addressable LocationsSpecial Function Registers Special Function Register SFR Memory MapSpecial Function Registers Register Address DescriptionADC0L REF0CN PSWSPI0CN Register Descriptions SFR Definition 9.1. DPL Data Pointer Low ByteSFR Definition 9.2. DPH Data Pointer High Byte SFR Definition 9.3. SP Stack PointerRegister Bank Address SFR Definition 9.4. PSW Program Status WordSFR Definition 9.5. ACC Accumulator RS1 RS0External Interrupts SFR Definition 9.6. B B RegisterInterrupt Handler MCU Interrupt Sources and VectorsIT1 IN1PL Interrupt PrioritiesInterrupt Latency IT0 IN0PLInterrupt Register Descriptions Interrupt SummaryESPI0 ET2 ES0 ET1 EX1 ET0 EX0 SFR Definition 9.7. IE Interrupt EnablePSPI0 PT2 PS0 PT1 PX1 PT0 PX0 SFR Definition 9.8. IP Interrupt PriorityET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 EUSB0 ESMB0 SFR Definition 9.9. EIE1 Extended Interrupt EnablePT3 PCP1 PCP0 PPCA0 PADC0 PWADC0 PUSB0 PSMB0 SFR Definition 9.10. EIP1 Extended Interrupt PriorityPS1 Pvbus SFR Definition 9.11. EIE2 Extended Interrupt EnableSFR Definition 9.12. EIP2 Extended Interrupt Priority ES1 EvbusIN0SL2-0 INT0 Port Pin SFR Definition 9.13. IT01CF INT0/INT1 ConfigurationIN1PL IN1SL2 IN1SL1 IN1SL0 IN0PL IN0SL2 IN0SL1 IN0SL0 IN1SL2-0 INT1 Port PinPower Management Modes Idle ModeStop Mode GF5 GF4 GF3 GF2 GF1 GF0 Stop Idle SFR Definition 9.14. Pcon Power ControlC8051F340/1/2/3/4/5/6/7 Prefetch Engine SFR Definition 10.1. PFE0CN Prefetch Engine ControlPfen Flbwe 100 Reset Sources Power-On and VDD Monitor Reset Timing Power-On ResetPower-Fail Reset / VDD Monitor SFR Definition 11.1. VDM0CN VDD Monitor ControlVdmen PCA Watchdog Timer Reset External ResetMissing Clock Detector Reset Comparator0 ResetUSB Reset Software ResetUsbrsf Ferror C0RSEF Swrsf Wdtrsf Mcdrsf Porsf Pinrsf SFR Definition 11.2. Rstsrc Reset SourceReset Electrical Characteristics 108 Flash Lock and Key Functions Flash Erase ProcedureFlash Memory Programming The Flash MemoryFlash Write Procedure Flash Electrical Characteristics Non-volatile Data StorageSecurity Options Flash Program Memory Map and Security Byte Accessing Flash from the C2 debug interface SFR Definition 12.1. Psctl Program Store R/W Control SFR Definition 12.2. Flkey Flash Lock and KeyPswe SFR Definition 12.3. Flscl Flash Scale FoseFlrt 116 Accessing Xram External Data Memory Interface and On-Chip XramBit Movx Example USB Fifo Space Accessing USB Fifo SpacePort Configuration Configuring the External Memory InterfacePGSEL7 PGSEL6 PGSEL5 PGSEL4 PGSEL3 PGSEL2 PGSEL1 PGSEL0 Usbfae EMD2 EMD1 EMD0 EALE1 EALE0 SFR Definition 13.2. EMI0CF External Memory ConfigurationMultiplexed and Non-multiplexed Selection Multiplexed ConfigurationNon-multiplexed Configuration Non-multiplexed Configuration Example Memory Mode SelectionInternal Xram Only Split Mode without Bank SelectSplit Mode with Bank Select TimingExternal Only EAS1 EAS0 ERW3 EWR2 EWR1 EWR0 EAH1 EAH0 SFR Definition 13.3. EMI0TC External Memory Timing ControlEmif Read Data Non-multiplexed ModeBit Movx EMI0CF42 = ‘101’, ‘110’, or ‘111’ Emif Write DataBit Movx without Bank Select EMI0CF42 = ‘101’ or ‘111’ Non-multiplexed 8-bit Movx without Bank Select TimingBit Movx with Bank Select EMI0CF42 = ‘110’ Non-multiplexed 8-bit Movx with Bank Select TimingBit Movx EMI0CF42 = ‘001’, ‘010’, or ‘011’ Multiplexed ModeBit Movx without Bank Select EMI0CF42 = ‘001’ or ‘011’ Multiplexed 8-bit Movx without Bank Select TimingBit Movx with Bank Select EMI0CF42 = ‘010’ 10. Multiplexed 8-bit Movx with Bank Select TimingParameter Description Min Max Units AC Parameters for External Memory Interface134 Oscillators Oscillator DiagramIoscen Ifrdy Suspend IFCN1 IFCN0 Internal H-F Oscillator Suspend ModeProgrammable Internal High-Frequency H-F Oscillator SFR Definition 14.1. Oscicn Internal H-F Oscillator ControlProgrammable Internal Low-Frequency L-F Oscillator Calibrating the Internal L-F OscillatorOsccal Osclen Osclrdy OSCLF3 OSCLF2 OSCLF1 OSCLF0 OSCLD1 OSCLD0 SFR Definition 14.3. Osclcn Internal L-F Oscillator ControlClocking Timers Directly Through the External Oscillator External Oscillator Drive CircuitExternal Crystal Example External Capacitor Example External RC ExampleSFR Definition 14.4. Oscxcn External Oscillator Control Xtlvld XOSCMD2 XOSCMD1 XOSCMD0 XFCN2 XFCN1 XFCN0Xfcn Mulsel Clock MultiplierSFR Definition 14.5. Clkmul Clock Multiplier Control Mulen Mulinit Mulrdy MulselSystem Clock Selection External Oscillator Clock SignalInternal Oscillator Clock Signal System and USB Clock SelectionClksl SFR Definition 14.6. Clksel Clock SelectUsbclk Clksl UsbclkExternal USB Clock Requirements Oscillator Electrical Characteristics146 Port Input/Output Port I/O Functional Block Diagram Port 0 through PortPort I/O Cell Block Diagram Priority Crossbar Decoder Crossbar Priority Decoder with No Pins SkippedCrossbar Priority Decoder with Crystal Pins Skipped Port I/O Initialization CP1AE CP1E CP0AE CP0E Syscke SMB0E SPI0E URT0E SFR Definition 15.1. XBR0 Port I/O Crossbar RegisterURT1E SFR Definition 15.2. XBR1 Port I/O Crossbar RegisterSFR Definition 15.3. XBR2 Port I/O Crossbar Register Weakpud Xbare T1E T0E Ecie PCA0MESFR Definition 15.5. P0MDIN Port0 Input Mode General Purpose Port I/OSFR Definition 15.4. P0 Port0 Latch SFR Definition 15.7. P0SKIP Port0 Skip SFR Definition 15.6. P0MDOUT Port0 Output ModeSFR Definition 15.9. P1MDIN Port1 Input Mode SFR Definition 15.10. P1MDOUT Port1 Output ModeSFR Definition 15.8. P1 Port1 Latch SFR Definition 15.13. P2MDIN Port2 Input Mode SFR Definition 15.11. P1SKIP Port1 SkipSFR Definition 15.12. P2 Port2 Latch SFR Definition 15.15. P2SKIP Port2 Skip SFR Definition 15.14. P2MDOUT Port2 Output ModeSFR Definition 15.17. P3MDIN Port3 Input Mode SFR Definition 15.18. P3MDOUT Port3 Output ModeSFR Definition 15.16. P3 Port3 Latch SFR Definition 15.20. P4 Port4 Latch SFR Definition 15.19. P3SKIP Port3 SkipSFR Definition 15.22. P4MDOUT Port4 Output Mode SFR Definition 15.21. P4MDIN Port4 Input ModePort I/O DC Electrical Characteristics Universal Serial Bus Controller USB0 USB0 Block DiagramEndpoint Associated Pipes USB Protocol Address Endpoint AddressingEndpoint Addressing Scheme USB TransceiverSFR Definition 16.1. USB0XCN USB0 Transceiver Control Pren Phyen Speed PHYTST1 PHYTST0 DfrecPHYTST10 USB0 Register Access Scheme USB Register AccessBusy Autord Usbaddr SFR Definition 16.2. USB0ADR USB0 Indirect AddressSFR Definition 16.3. USB0DAT USB0 Data USB0 Controller Registers USB Register Definition 16.4. Index USB0 Endpoint IndexIndex CRE Crssen Crlow USB Clock ConfigurationUSB Register Definition 16.5. Clkrec Clock Recovery Control Communication Speed USB Clock 4x Clock Multiplier InputFifo Management Fifo Split ModeFifodata Fifo ConfigurationsFifo Access Fifo Double BufferingFunction Configuration and Control Function AddressingUSB Register Definition 16.7. Faddr USB0 Function Address 174 Isoud Usbinh Usbrst Resume Susmd Susen USB Register Definition 16.8. Power USB0 PowerInterrupts USB Register Definition 16.9. Framel USB0 Frame Number LowOUT3 OUT2 OUT1 IN3 IN2 IN1 EP0SOF Rstint Rsuint Susint USB Register Definition 16.13. Cmint USB0 Common InterruptOUT3E OUT2E OUT1E IN3E IN2E IN1E EP0ESerial Interface Engine Endpoint0Sofe Rstinte Rsuinte Susinte Endpoint0 in Transactions Endpoint0 Setup TransactionsEndpoint0 OUT Transactions USB Register Definition 16.17. E0CSR USB0 Endpoint0 Control Ssuend Soprdy Sdstl Suend Dataend Ststl Inprdy OprdySsuend Configuring Endpoints1-3 Endpoints1-3 in Interrupt or Bulk ModeControlling Endpoints1-3 Endpoints1-3 in Isochronous Mode A packet being transmitted Clrdt Ststl Sdstl Flush Undrun Fifone InprdyEndpoints1-3 OUT Interrupt or Bulk Mode Controlling Endpoints1-3 OUTDbien ISO Dirsel Fcdt Split Endpoints1-3 OUT Isochronous Mode Clrdt Ststl Sdstl Flush Daterr Ovrun Fifoful Oprdy Dboen ISO EoclE0CH Receiver USB Transceiver Electrical Characteristics192 SMBus SMBus Block DiagramSupporting Documents SMBus ConfigurationArbitration SMBus TransactionClock Low Extension Using the SMBusSCL Low Timeout SCL High SMBus Free TimeoutTion Register on Equation 17.2. Typical SMBus Bit Rate SMBus Configuration RegisterSMBus Clock Source Selection Equation 17.1. Minimum SCL High and Low TimesMinimum SDA Setup and Hold Times Minimum SDA Setup Time Minimum SDA Hold TimeExthold Ensmb INH Busy Exthold Smbtoe Smbfte SMBCS1 SMBCS0 SFR Definition 17.1. SMB0CF SMBus Clock/ConfigurationSMB0CN Control Register Master Txmode STA STO Ackrq Arblost ACK SFR Definition 17.2. SMB0CN SMBus ControlSources for Hardware Changes to SMB0CN Bit Set by Hardware When Cleared by Hardware WhenData Register Master Transmitter ModeSFR Definition 17.3. SMB0DAT SMBus Data SMBus Transfer ModesTypical Master Transmitter Sequence Typical Master Receiver Sequence Master Receiver ModeTypical Slave Receiver Sequence Slave Receiver ModeTypical Slave Transmitter Sequence SMBus Status Decoding Slave Transmitter ModeValues Read Current SMbus State Typical Response OptionsStart Slave byte was transmitted No action required expect UART0 UART0 Block DiagramEnhanced Baud Rate Generation Equation 18.1. UART0 Baud RateOperational Modes Bit Uart Uart Interconnect DiagramBit Uart Timing Diagram Multiprocessor Communications Master Slave Device SFR Definition 18.1. SCON0 Serial Port 0 Control S0MODE MCE0 REN0TI0 RI0 SFR Definition 18.2. SBUF0 Serial UART0 Port Data Buffer Rate bps Factor Select Target Actual Baud Oscillator Timer ClockT1M Timer Baud Rate Error Divide Source Pre-scale SCA1-SCA0UART1 C8051F340/1/4/5 Only UART1 Block DiagramSBRLH1SBRLL1 Baud Rate Generator Settings for Standard Baud RatesBaud Rate Generator Equation 19.1. UART1 Baud RateUART1 Timing Without Parity or Extra Bit Data FormatConfiguration and Operation Data TransmissionData Reception Multiprocessor Communications SFR Definition 19.1. SCON1 UART1 Control OVR1 PERR1 THRE1 REN1 TBX1 RBX1 TI1 RI1Fifo MCE1 S1PT1 S1PT0 PE1 S1DL1 S1DL0 XBE1 SBL1 SFR Definition 19.2. SMOD1 UART1 ModeSFR Definition 19.3. SBUF1 UART1 Data Buffer SB1RUNSB1PS1 SB1PS0 Rev 227 228 Enhanced Serial Peripheral Interface SPI0 SPI Block DiagramSerial Clock SCK Signal DescriptionsMaster Out, Slave In Mosi Master In, Slave Out MisoSPI0 Master Mode Operation Multiple-Master Mode Connection Diagram SPI0 Interrupt Sources SPI0 Slave Mode OperationSerial Clock Timing Master Mode Data/Clock TimingSlave Mode Data/Clock Timing Ckpha = SFR Definition 20.1. SPI0CFG SPI0 Configuration SPI Special Function RegistersSpibsy Msten Ckpha Ckpol Slvsel Nssin Srmt Rxbmt Spif Wcol Modf Rxovrn NSSMD1 NSSMD0 Txbmt Spien SFR Definition 20.2. SPI0CN SPI0 ControlSFR Definition 20.3. SPI0CKR SPI0 Clock Rate SFR Definition 20.4. SPI0DAT SPI0 DataSCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SPI Master Timing Ckpha = 10. SPI Slave Timing Ckpha = Slave Mode Timing* See Figure SPI Slave Timing ParametersOnly 242 Timer 0 and Timer 1 Modes Timer 2 Modes Timer 3 Modes TimersTimer 0 and Timer Mode 0 13-bit Counter/TimerMode 1 16-bit Counter/Timer Counter/TimerTR0 GATE0 INT0 Mode 2 8-bit Counter/Timer with Auto-Reload T0 Mode 2 Block DiagramMode 3 Two 8-bit Counter/Timers Timer 0 Only T0 Mode 3 Block DiagramTF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SFR Definition 21.1. Tcon Timer ControlT1M1 T1M0 SFR Definition 21.2. Tmod Timer ModeGATE1 GATE0Prescaled Clock SFR Definition 21.3. Ckcon Clock ControlT3MH T3ML T2MH T2ML T1M T0M SCA1 SCA0 SCA1 SCA0SFR Definition 21.7. TH1 Timer 1 High Byte SFR Definition 21.4. TL0 Timer 0 Low ByteSFR Definition 21.5. TL1 Timer 1 Low Byte SFR Definition 21.6. TH0 Timer 0 High ByteBit Timer with Auto-Reload TimerT2ML T2XCLK Bit Timers with Auto-ReloadT2MH T2XCLK TMR2H Clock SourceTimer 2 Capture Mode T2SPLIT = ‘0’ Timer 2 Capture Mode T2SPLIT = ‘1’ TF2H TF2L TF2LEN T2CE T2SPLIT TR2 T2CSS T2XCLK SFR Definition 21.8. TMR2CN Timer 2 ControlSFR Definition 21.12. TMR2H Timer 2 High Byte SFR Definition 21.11. TMR2L Timer 2 Low ByteTimer 3 16-Bit Mode Block Diagram TMR3L Clock Source T3MH T3XCLKTMR3H Clock Source T3ML T3XCLKUSB Start-of-Frame Capture 10. Timer 3 Capture Mode T3SPLIT = ‘0’11. Timer 3 Capture Mode T3SPLIT = ‘1’ TF3H TF3L TF3LEN T3CE T3SPLIT TR3 T3CSS T3XCLK SFR Definition 21.13. TMR3CN Timer 3 ControlSFR Definition 21.17. TMR3H Timer 3 High Byte SFR Definition 21.16. TMR3L Timer 3 Low ByteProgrammable Counter Array PCA0 Timebase PCA Counter/TimerPCA Timebase Input Options CPS2 CPS1 CPS0PWM16 Ecom Capp Capn MAT TOG Eccf PCA0CPM Register Settings for PCA Capture/Compare ModulesOperation Mode Capture/Compare ModulesEdge-triggered Capture Mode PCA Capture Mode DiagramSoftware Timer Compare Mode PCA Software Timer Mode DiagramHigh Speed Output Mode PCA High Speed Output Mode DiagramEquation 22.1. Square Wave Frequency Output Frequency Output ModeEquation 22.2 -Bit PWM Duty Cycle Bit Pulse Width Modulator ModeEquation 22.3 -Bit PWM Duty Cycle PCA 16-Bit PWM ModeWatchdog Timer Operation Watchdog Timer ModePCA0CPL4 Equation 22.4. Watchdog Timer Offset in PCA ClocksWatchdog Timer Timeout Intervals1 Watchdog Timer UsageRegister Descriptions for PCA SFR Definition 22.1. PCA0CN PCA ControlCCF4 CCF3 CCF2 CCF1 CCF0 Cidl Wdte Wdlck CPS2 CPS1 CPS0 ECF SFR Definition 22.2. PCA0MD PCA ModeSFR Definition 22.3. PCA0CPMn PCA Capture/Compare Mode SFR Definition 22.4. PCA0L PCA Counter/Timer Low Byte SFR Definition 22.5. PCA0H PCA Counter/Timer High ByteSFR Definition 22.6. PCA0CPLn PCA Capture Module Low Byte SFR Definition 22.7. PCA0CPHn PCA Capture Module High Byte C2 Register Definition 23.2. Deviceid C2 Device ID 23. C2 Interface23.1. C2 Interface Registers C2 Register Definition 23.1. C2ADD C2 AddressC2 Register Definition 23.3. Revid C2 Revision ID Code CommandTypical C2 Pin Sharing 23.2. C2 Pin SharingContact Information