C8051F340/1/2/3/4/5/6/7
19. UART1 (C8051F340/1/4/5 Only)
UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a
UART1 has six associated SFRs. Three are used for the Baud Rate Generator (SBCON1, SBRLH1, and SBRLL1), two are used for data formatting, control, and status functions (SCON1, SMOD1), and one is used to send and receive data (SBUF1). The single SBUF1 location provides access to both the transmit holding register and the receive FIFO. Writes to SBUF1 always access the Transmit Holding Register.
Reads of SBUF1 always access the first byte of the Receive FIFO; it is not possible to read data from the Transmit Holding Register.
With UART1 interrupts enabled, an interrupt is generated each time a transmit is completed (TI1 is set in SCON1), or a data byte has been received (RI1 is set in SCON1). The UART1 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART1 interrupt (transmit complete or receive complete). Note that if additional bytes are available in the Receive FIFO, the RI1 bit cannot be cleared by software.
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| Baud Rate Generator | |
| SBRLH1 | SBRLL1 | Overflow |
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SYSCLK | Timer | ||
| (1, 4, 12, 48) | ||
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| EN | |
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| SB1RUN | SB1PS1 SB1PS0 |
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| SBCON1 |
Data Formatting
SMOD1
MCE1S1PT1S1PT0PE1S1DL1S1DL0XBE1SBL1
Control / Status | |||
| SCON1 |
|
|
OVR1 PERR1 | THRE1 REN1 TBX1 RBX1 | TI1 | RI1 |
UART1
Interrupt
TX | TX1 | |
Logic | ||
|
TX Holding
Register
Write to SBUF1 SBUF1
Read of SBUF1
RX FIFO (3 Deep)
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|
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RX |
|
| RX1 | |
Logic |
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Figure 19.1. UART1 Block Diagram
Rev. 0.5 | 219 |
