Silicon Laboratories C8051F342, C8051F347 SFR Definition 16.2. USB0ADR USB0 Indirect Address

C8051F340/1/2/3/4/5/6/7

SFR Definition 16.2. USB0ADR: USB0 Indirect Address

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

BUSY	AUTORD			USBADDR
Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0

00000000

SFR Address:

	0x96
Bits7:	BUSY: USB0 Register Read Busy Flag
	This bit is used during indirect USB0 register accesses. Software should write ‘1’ to this bit to
	initiate a read of the USB0 register targeted by the USBADDR bits (USB0ADR.[5-0]). The
	target address and BUSY bit may be written in the same write to USB0ADR. After BUSY is
	set to ‘1’, hardware will clear BUSY when the targeted register data is ready in the
	USB0DAT register. Software should check BUSY for ‘0’ before writing to USB0DAT.
	Write:
	0: No effect.
	1: A USB0 indirect register read is initiated at the address specified by the USBADDR bits.
	Read:
	0: USB0DAT register data is valid.
	1: USB0 is busy accessing an indirect register; USB0DAT register data is invalid.
Bit6:	AUTORD: USB0 Register Auto-read Flag
	This bit is used for block FIFO reads.
	0: BUSY must be written manually for each USB0 indirect register read.
	1: The next indirect register read will automatically be initiated when software reads
	USB0DAT (USBADDR bits will not be changed).
Bits5–0:	USBADDR: USB0 Indirect Register Address
	These bits hold a 6-bit address used to indirectly access the USB0 core registers. Table 16.2
	lists the USB0 core registers and their indirect addresses. Reads and writes to USB0DAT
	will target the register indicated by the USBADDR bits.

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