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Silicon Laboratories C8051F346, C8051F347, C8051F341 Voltage Regulator, On-Chip Debug Circuitry

Models: C8051F346 C8051F347 C8051F344 C8051F342 C8051F343 C8051F345 C8051F340 C8051F341

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C8051F340/1/2/3/4/5/6/7

1.4.Voltage Regulator

C8051F340/1/2/3/4/5/6/7 devices include a voltage regulator (REG0). When enabled, the REG0 output appears on the VDD pin, and can also be used to power other external devices. REG0 can be enabled/dis- abled by software.

1.5.On-Chip Debug Circuitry

The C8051F340/1/2/3/4/5/6/7 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that pro- vides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application.

Silicon Labs' debugging system supports inspection and modification of memory and registers, break- points, and single stepping. No additional target RAM, program memory, timers, or communications chan- nels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the USB, ADC, and SMBus) are stalled when the MCU is halted, during sin- gle stepping, or at a breakpoint in order to keep them synchronized.

The C8051F340DK development kit provides all the hardware and software necessary to develop applica- tion code and perform in-circuit debugging with the C8051F340/1/2/3/4/5/6/7 MCUs. The kit includes soft- ware with a developer's studio and debugger, 8051 assembler and linker, evaluation ‘C’ compiler, and a debug adapter. It also has a target application board with the C8051F340 MCU installed, the necessary cables for connection to a PC, and a wall-mount power supply. The development kit contents may also be used to program and debug the device on the production PCB using the appropriate connections for the programming pins.

The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the precision analog peripherals.

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Silicon Laboratories C8051F346, C8051F347, C8051F341, C8051F343, C8051F340 Voltage Regulator, On-Chip Debug Circuitry

Contents

Precision Internal Oscillators Full Speed USB Flash MCU FamilyHIGH-SPEED Controller Core Rev Table Of Contents Flash Memory 109 Prefetch Engine Reset Sources 101External Data Memory Interface and On-Chip Xram 117 Port Input/Output 147 Oscillators 135Universal Serial Bus Controller USB0 163 SMBus 193UART0 211 Timers 243UART1 C8051F340/1/4/5 Only 219 Enhanced Serial Peripheral Interface SPI0 22923. C2 Interface 279 Programmable Counter Array PCA0 263Contact Information 282 C8051F340/1/2/3/4/5/6/7 Absolute Maximum Ratings List of Figures and TablesVoltage Reference Flash Memory Prefetch Engine Reset SourcesExternal Data Memory Interface and On-Chip Xram OscillatorsUART0 SMBusUART1 C8051F340/1/4/5 Only Enhanced Serial Peripheral Interface SPI0Programmable Counter Array PCA0 Timers23.C2 Interface List of Registers C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 System Overview RAM Product Selection GuideTQFP48 LQFP32C8051F340/1/4/5 Block Diagram C8051F342/3/6/7 Block Diagram CIP-51 Microcontroller Core Additional FeaturesFully 8051 Compatible Improved ThroughputOn-Chip Clock and Reset On-Chip Memory Map for 64kB Devices C8051F340/2/4/6 On-Chip MemoryUniversal Serial Bus Controller USB Controller Block DiagramOn-Chip Debug Circuitry Voltage RegulatorProgrammable Digital I/O and Crossbar Digital Crossbar DiagramProgrammable Counter Array Serial PortsBit Analog to Digital Converter Bit ADC Block Diagram10. Comparator0 Block Diagram Parameter Conditions Min Typ Max Units Absolute Maximum RatingsGND TBD Global DC Electrical CharacteristicsIndex to Electrical Characteristics Tables Table Title Pin Definitions for the C8051F340/1/2/3/4/5/6/7 Pinout and Package DefinitionsName Pin Numbers Type Description 48-pin 32-pin C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 C8051F340/1/4/5 Top View TQFP-48 Package DimensionsMIN TYP MAX GND VDD Regin Vbus LQFP-32 Pinout Diagram Top ViewLQFP-32 LQFP-32 Package DiagramC8051F340/1/2/3/4/5/6/7 Bit ADC ADC0 ADC0 Functional Block DiagramVref Analog MultiplexerTemperature Sensor Transfer Function Temperature SensorTemperature degrees C Starting a Conversion Modes of OperationTracking Modes Bit ADC Track and Conversion Example TimingEquation 5.1. ADC0 Settling Time Requirements Differential Mode Single-Ended ModeSettling Time Requirements AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 SFR Definition 5.1. AMX0P AMUX0 Positive Channel SelectAMX0P4-0 ADC0 Positive Input Pin Package ReservedAMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 SFR Definition 5.2. AMX0N AMUX0 Negative Channel SelectAMX0N4-0 ADC0 Negative Input Pin Package SFR Definition 5.4. ADC0H ADC0 Data Word MSB SFR Definition 5.3. ADC0CF ADC0 ConfigurationSFR Definition 5.5. ADC0L ADC0 Data Word LSB AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0LJSTAD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 SFR Definition 5.6. ADC0CN ADC0 ControlSFR Definition 5.8. ADC0GTL ADC0 Greater-Than Data Low Byte Programmable Window DetectorSFR Definition 5.10. ADC0LTL ADC0 Less-Than Data Low Byte SFR Definition 5.9. ADC0LTH ADC0 Less-Than Data High ByteADC Window Compare Example Right-Justified Single-Ended Data Window Detector In Single-Ended ModeADC Window Compare Example Right-Justified Differential Data Window Detector In Differential ModeConversion Rate ADC0 Electrical CharacteristicsAnalog Inputs Voltage Reference Voltage Reference Functional Block DiagramSFR Definition 6.1. REF0CN Reference Control Voltage Reference Electrical CharacteristicsRefsl Tempe Biase Refbe External Reference Refbe =Comparators Comparator Functional Block Diagram Comparator Hysteresis Plot CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 SFR Definition 7.1. CPT0CN Comparator0 ControlCMX0N1 CMX0N0 SFR Definition 7.2. CPT0MX Comparator0 MUX SelectionNegative Input Pin Package CMX0P1 CMX0P0CP0RIE CP0FIE CP0MD1 CP0MD0 SFR Definition 7.3. CPT0MD Comparator0 Mode SelectionMode CP0MD1 CP0MD0CP1EN CP1OUT CP1RIF CP1FIF SFR Definition 7.4. CPT1CN Comparator1 ControlCMX1N2 CMX1N1 CMX1N0 CMX1P2 CMX1P1 CMX1P0 SFR Definition 7.5. CPT1MX Comparator1 MUX SelectionCMX1N2 CMX1N1 CMX1N0 CMX1P2 CMX1P1 CMX1P0CP1RIE CP1FIE CP1MD1 CP1MD0 SFR Definition 7.6. CPT1MD Comparator1 Mode SelectionCP1MD1 CP1MD0 CP1 Response TimeComparator Electrical Characteristics Voltage Regulator Electrical Specifications Regulator Mode SelectionVoltage Regulator REG0 Vbus DetectionREG0 Configuration USB Bus-Powered REG0 Configuration USB Self-Powered, Regulator Disabled Regdis Vbstat Vbpol Regmod SFR Definition 8.1. REG0CN Voltage Regulator ControlCIP-51 Microcontroller CIP-51 Block DiagramInstruction and CPU Timing Instruction SetPerformance Movx Instruction and Program Memory CIP-51 Instruction Set SummaryLogical Operations Data Transfer Mnemonic Description Bytes Clock CyclesProgram Branching Boolean ManipulationC8051F340/1/2/3/4/5/6/7 Program Memory Memory OrganizationGeneral Purpose Registers Data MemoryBit Addressable Locations StackSpecial Function Registers Special Function Register SFR Memory MapRegister Address Description Special Function RegistersADC0L REF0CN PSWSPI0CN SFR Definition 9.2. DPH Data Pointer High Byte SFR Definition 9.1. DPL Data Pointer Low ByteSFR Definition 9.3. SP Stack Pointer Register DescriptionsSFR Definition 9.5. ACC Accumulator SFR Definition 9.4. PSW Program Status WordRS1 RS0 Register Bank AddressInterrupt Handler SFR Definition 9.6. B B RegisterMCU Interrupt Sources and Vectors External InterruptsInterrupt Latency Interrupt PrioritiesIT0 IN0PL IT1 IN1PLInterrupt Register Descriptions Interrupt SummaryESPI0 ET2 ES0 ET1 EX1 ET0 EX0 SFR Definition 9.7. IE Interrupt EnablePSPI0 PT2 PS0 PT1 PX1 PT0 PX0 SFR Definition 9.8. IP Interrupt PriorityET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 EUSB0 ESMB0 SFR Definition 9.9. EIE1 Extended Interrupt EnablePT3 PCP1 PCP0 PPCA0 PADC0 PWADC0 PUSB0 PSMB0 SFR Definition 9.10. EIP1 Extended Interrupt PrioritySFR Definition 9.12. EIP2 Extended Interrupt Priority SFR Definition 9.11. EIE2 Extended Interrupt EnableES1 Evbus PS1 PvbusIN1PL IN1SL2 IN1SL1 IN1SL0 IN0PL IN0SL2 IN0SL1 IN0SL0 SFR Definition 9.13. IT01CF INT0/INT1 ConfigurationIN1SL2-0 INT1 Port Pin IN0SL2-0 INT0 Port PinIdle Mode Power Management ModesStop Mode GF5 GF4 GF3 GF2 GF1 GF0 Stop Idle SFR Definition 9.14. Pcon Power ControlC8051F340/1/2/3/4/5/6/7 SFR Definition 10.1. PFE0CN Prefetch Engine Control Prefetch EnginePfen Flbwe 100 Reset Sources Power-On and VDD Monitor Reset Timing Power-On ResetSFR Definition 11.1. VDM0CN VDD Monitor Control Power-Fail Reset / VDD MonitorVdmen Missing Clock Detector Reset External ResetComparator0 Reset PCA Watchdog Timer ResetUSB Reset Software ResetUsbrsf Ferror C0RSEF Swrsf Wdtrsf Mcdrsf Porsf Pinrsf SFR Definition 11.2. Rstsrc Reset SourceReset Electrical Characteristics 108 Flash Memory Flash Erase ProcedureProgramming The Flash Memory Flash Lock and Key FunctionsFlash Write Procedure Non-volatile Data Storage Flash Electrical CharacteristicsSecurity Options Flash Program Memory Map and Security Byte Accessing Flash from the C2 debug interface SFR Definition 12.2. Flkey Flash Lock and Key SFR Definition 12.1. Psctl Program Store R/W ControlPswe Fose SFR Definition 12.3. Flscl Flash ScaleFlrt 116 External Data Memory Interface and On-Chip Xram Accessing XramBit Movx Example USB Fifo Space Accessing USB Fifo SpacePort Configuration Configuring the External Memory InterfacePGSEL7 PGSEL6 PGSEL5 PGSEL4 PGSEL3 PGSEL2 PGSEL1 PGSEL0 Usbfae EMD2 EMD1 EMD0 EALE1 EALE0 SFR Definition 13.2. EMI0CF External Memory ConfigurationMultiplexed and Non-multiplexed Selection Multiplexed ConfigurationNon-multiplexed Configuration Non-multiplexed Configuration Example Memory Mode SelectionInternal Xram Only Split Mode without Bank SelectTiming Split Mode with Bank SelectExternal Only EAS1 EAS0 ERW3 EWR2 EWR1 EWR0 EAH1 EAH0 SFR Definition 13.3. EMI0TC External Memory Timing ControlBit Movx EMI0CF42 = ‘101’, ‘110’, or ‘111’ Non-multiplexed ModeEmif Write Data Emif Read DataBit Movx without Bank Select EMI0CF42 = ‘101’ or ‘111’ Non-multiplexed 8-bit Movx without Bank Select TimingBit Movx with Bank Select EMI0CF42 = ‘110’ Non-multiplexed 8-bit Movx with Bank Select TimingBit Movx EMI0CF42 = ‘001’, ‘010’, or ‘011’ Multiplexed ModeBit Movx without Bank Select EMI0CF42 = ‘001’ or ‘011’ Multiplexed 8-bit Movx without Bank Select TimingBit Movx with Bank Select EMI0CF42 = ‘010’ 10. Multiplexed 8-bit Movx with Bank Select TimingParameter Description Min Max Units AC Parameters for External Memory Interface134 Oscillators Oscillator DiagramProgrammable Internal High-Frequency H-F Oscillator Internal H-F Oscillator Suspend ModeSFR Definition 14.1. Oscicn Internal H-F Oscillator Control Ioscen Ifrdy Suspend IFCN1 IFCN0Calibrating the Internal L-F Oscillator Programmable Internal Low-Frequency L-F OscillatorOsccal Osclen Osclrdy OSCLF3 OSCLF2 OSCLF1 OSCLF0 OSCLD1 OSCLD0 SFR Definition 14.3. Osclcn Internal L-F Oscillator ControlExternal Oscillator Drive Circuit Clocking Timers Directly Through the External OscillatorExternal Crystal Example External Capacitor Example External RC ExampleXtlvld XOSCMD2 XOSCMD1 XOSCMD0 XFCN2 XFCN1 XFCN0 SFR Definition 14.4. Oscxcn External Oscillator ControlXfcn SFR Definition 14.5. Clkmul Clock Multiplier Control Clock MultiplierMulen Mulinit Mulrdy Mulsel MulselInternal Oscillator Clock Signal External Oscillator Clock SignalSystem and USB Clock Selection System Clock SelectionUsbclk Clksl SFR Definition 14.6. Clksel Clock SelectUsbclk ClkslExternal USB Clock Requirements Oscillator Electrical Characteristics146 Port Input/Output Port I/O Functional Block Diagram Port 0 through PortPort I/O Cell Block Diagram Priority Crossbar Decoder Crossbar Priority Decoder with No Pins SkippedCrossbar Priority Decoder with Crystal Pins Skipped Port I/O Initialization CP1AE CP1E CP0AE CP0E Syscke SMB0E SPI0E URT0E SFR Definition 15.1. XBR0 Port I/O Crossbar RegisterSFR Definition 15.3. XBR2 Port I/O Crossbar Register SFR Definition 15.2. XBR1 Port I/O Crossbar RegisterWeakpud Xbare T1E T0E Ecie PCA0ME URT1EGeneral Purpose Port I/O SFR Definition 15.5. P0MDIN Port0 Input ModeSFR Definition 15.4. P0 Port0 Latch SFR Definition 15.7. P0SKIP Port0 Skip SFR Definition 15.6. P0MDOUT Port0 Output ModeSFR Definition 15.10. P1MDOUT Port1 Output Mode SFR Definition 15.9. P1MDIN Port1 Input ModeSFR Definition 15.8. P1 Port1 Latch SFR Definition 15.11. P1SKIP Port1 Skip SFR Definition 15.13. P2MDIN Port2 Input ModeSFR Definition 15.12. P2 Port2 Latch SFR Definition 15.15. P2SKIP Port2 Skip SFR Definition 15.14. P2MDOUT Port2 Output ModeSFR Definition 15.18. P3MDOUT Port3 Output Mode SFR Definition 15.17. P3MDIN Port3 Input ModeSFR Definition 15.16. P3 Port3 Latch SFR Definition 15.20. P4 Port4 Latch SFR Definition 15.19. P3SKIP Port3 SkipSFR Definition 15.22. P4MDOUT Port4 Output Mode SFR Definition 15.21. P4MDIN Port4 Input ModePort I/O DC Electrical Characteristics Universal Serial Bus Controller USB0 USB0 Block DiagramEndpoint Addressing Scheme Endpoint AddressingUSB Transceiver Endpoint Associated Pipes USB Protocol AddressPren Phyen Speed PHYTST1 PHYTST0 Dfrec SFR Definition 16.1. USB0XCN USB0 Transceiver ControlPHYTST10 USB0 Register Access Scheme USB Register AccessBusy Autord Usbaddr SFR Definition 16.2. USB0ADR USB0 Indirect AddressSFR Definition 16.3. USB0DAT USB0 Data USB Register Definition 16.4. Index USB0 Endpoint Index USB0 Controller RegistersIndex USB Register Definition 16.5. Clkrec Clock Recovery Control USB Clock ConfigurationCommunication Speed USB Clock 4x Clock Multiplier Input CRE Crssen CrlowFifo Management Fifo Split ModeFifo Access Fifo ConfigurationsFifo Double Buffering FifodataFunction Addressing Function Configuration and ControlUSB Register Definition 16.7. Faddr USB0 Function Address 174 Isoud Usbinh Usbrst Resume Susmd Susen USB Register Definition 16.8. Power USB0 PowerInterrupts USB Register Definition 16.9. Framel USB0 Frame Number LowOUT3 OUT2 OUT1 IN3 IN2 IN1 EP0SOF Rstint Rsuint Susint USB Register Definition 16.13. Cmint USB0 Common InterruptOUT3E OUT2E OUT1E IN3E IN2E IN1E EP0EEndpoint0 Serial Interface EngineSofe Rstinte Rsuinte Susinte Endpoint0 in Transactions Endpoint0 Setup TransactionsEndpoint0 OUT Transactions Ssuend Soprdy Sdstl Suend Dataend Ststl Inprdy Oprdy USB Register Definition 16.17. E0CSR USB0 Endpoint0 ControlSsuend Endpoints1-3 in Interrupt or Bulk Mode Configuring Endpoints1-3Controlling Endpoints1-3 Endpoints1-3 in Isochronous Mode A packet being transmitted Clrdt Ststl Sdstl Flush Undrun Fifone InprdyControlling Endpoints1-3 OUT Endpoints1-3 OUT Interrupt or Bulk ModeDbien ISO Dirsel Fcdt Split Endpoints1-3 OUT Isochronous Mode Clrdt Ststl Sdstl Flush Daterr Ovrun Fifoful Oprdy Eocl Dboen ISOE0CH Receiver USB Transceiver Electrical Characteristics192 SMBus SMBus Block DiagramSupporting Documents SMBus ConfigurationArbitration SMBus TransactionSCL Low Timeout Using the SMBusSCL High SMBus Free Timeout Clock Low ExtensionTion Register on SMBus Clock Source Selection SMBus Configuration RegisterEquation 17.1. Minimum SCL High and Low Times Equation 17.2. Typical SMBus Bit RateMinimum SDA Setup Time Minimum SDA Hold Time Minimum SDA Setup and Hold TimesExthold Ensmb INH Busy Exthold Smbtoe Smbfte SMBCS1 SMBCS0 SFR Definition 17.1. SMB0CF SMBus Clock/ConfigurationSMB0CN Control Register Master Txmode STA STO Ackrq Arblost ACK SFR Definition 17.2. SMB0CN SMBus ControlSources for Hardware Changes to SMB0CN Bit Set by Hardware When Cleared by Hardware WhenSFR Definition 17.3. SMB0DAT SMBus Data Master Transmitter ModeSMBus Transfer Modes Data RegisterTypical Master Transmitter Sequence Typical Master Receiver Sequence Master Receiver ModeTypical Slave Receiver Sequence Slave Receiver ModeTypical Slave Transmitter Sequence SMBus Status Decoding Slave Transmitter ModeCurrent SMbus State Typical Response Options Values ReadStart Slave byte was transmitted No action required expect UART0 UART0 Block DiagramEquation 18.1. UART0 Baud Rate Enhanced Baud Rate GenerationOperational Modes Bit Uart Uart Interconnect DiagramBit Uart Timing Diagram Multiprocessor Communications Master Slave Device S0MODE MCE0 REN0 SFR Definition 18.1. SCON0 Serial Port 0 ControlTI0 RI0 SFR Definition 18.2. SBUF0 Serial UART0 Port Data Buffer T1M Timer Baud Rate Error Divide Source Pre-scale Target Actual Baud Oscillator Timer ClockSCA1-SCA0 Rate bps Factor SelectUART1 C8051F340/1/4/5 Only UART1 Block DiagramBaud Rate Generator Baud Rate Generator Settings for Standard Baud RatesEquation 19.1. UART1 Baud Rate SBRLH1SBRLL1UART1 Timing Without Parity or Extra Bit Data FormatData Transmission Configuration and OperationData Reception Multiprocessor Communications OVR1 PERR1 THRE1 REN1 TBX1 RBX1 TI1 RI1 SFR Definition 19.1. SCON1 UART1 ControlFifo MCE1 S1PT1 S1PT0 PE1 S1DL1 S1DL0 XBE1 SBL1 SFR Definition 19.2. SMOD1 UART1 ModeSB1RUN SFR Definition 19.3. SBUF1 UART1 Data BufferSB1PS1 SB1PS0 Rev 227 228 Enhanced Serial Peripheral Interface SPI0 SPI Block DiagramMaster Out, Slave In Mosi Signal DescriptionsMaster In, Slave Out Miso Serial Clock SCKSPI0 Master Mode Operation Multiple-Master Mode Connection Diagram SPI0 Interrupt Sources SPI0 Slave Mode OperationSerial Clock Timing Master Mode Data/Clock TimingSlave Mode Data/Clock Timing Ckpha = SPI Special Function Registers SFR Definition 20.1. SPI0CFG SPI0 ConfigurationSpibsy Msten Ckpha Ckpol Slvsel Nssin Srmt Rxbmt Spif Wcol Modf Rxovrn NSSMD1 NSSMD0 Txbmt Spien SFR Definition 20.2. SPI0CN SPI0 ControlSFR Definition 20.4. SPI0DAT SPI0 Data SFR Definition 20.3. SPI0CKR SPI0 Clock RateSCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SPI Master Timing Ckpha = 10. SPI Slave Timing Ckpha = SPI Slave Timing Parameters Slave Mode Timing* See FigureOnly 242 Timer 0 and Timer TimersMode 0 13-bit Counter/Timer Timer 0 and Timer 1 Modes Timer 2 Modes Timer 3 ModesCounter/Timer Mode 1 16-bit Counter/TimerTR0 GATE0 INT0 Mode 2 8-bit Counter/Timer with Auto-Reload T0 Mode 2 Block DiagramMode 3 Two 8-bit Counter/Timers Timer 0 Only T0 Mode 3 Block DiagramTF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SFR Definition 21.1. Tcon Timer ControlGATE1 SFR Definition 21.2. Tmod Timer ModeGATE0 T1M1 T1M0T3MH T3ML T2MH T2ML T1M T0M SCA1 SCA0 SFR Definition 21.3. Ckcon Clock ControlSCA1 SCA0 Prescaled ClockSFR Definition 21.5. TL1 Timer 1 Low Byte SFR Definition 21.4. TL0 Timer 0 Low ByteSFR Definition 21.6. TH0 Timer 0 High Byte SFR Definition 21.7. TH1 Timer 1 High ByteBit Timer with Auto-Reload TimerT2MH T2XCLK Bit Timers with Auto-ReloadTMR2H Clock Source T2ML T2XCLKTimer 2 Capture Mode T2SPLIT = ‘0’ Timer 2 Capture Mode T2SPLIT = ‘1’ TF2H TF2L TF2LEN T2CE T2SPLIT TR2 T2CSS T2XCLK SFR Definition 21.8. TMR2CN Timer 2 ControlSFR Definition 21.12. TMR2H Timer 2 High Byte SFR Definition 21.11. TMR2L Timer 2 Low ByteTimer 3 16-Bit Mode Block Diagram TMR3H Clock Source T3MH T3XCLKT3ML T3XCLK TMR3L Clock SourceUSB Start-of-Frame Capture 10. Timer 3 Capture Mode T3SPLIT = ‘0’11. Timer 3 Capture Mode T3SPLIT = ‘1’ TF3H TF3L TF3LEN T3CE T3SPLIT TR3 T3CSS T3XCLK SFR Definition 21.13. TMR3CN Timer 3 ControlSFR Definition 21.17. TMR3H Timer 3 High Byte SFR Definition 21.16. TMR3L Timer 3 Low ByteProgrammable Counter Array PCA0 PCA Timebase Input Options PCA Counter/TimerCPS2 CPS1 CPS0 TimebaseOperation Mode PCA0CPM Register Settings for PCA Capture/Compare ModulesCapture/Compare Modules PWM16 Ecom Capp Capn MAT TOG EccfEdge-triggered Capture Mode PCA Capture Mode DiagramSoftware Timer Compare Mode PCA Software Timer Mode DiagramHigh Speed Output Mode PCA High Speed Output Mode DiagramEquation 22.1. Square Wave Frequency Output Frequency Output ModeEquation 22.2 -Bit PWM Duty Cycle Bit Pulse Width Modulator ModeEquation 22.3 -Bit PWM Duty Cycle PCA 16-Bit PWM ModeWatchdog Timer Operation Watchdog Timer ModeWatchdog Timer Timeout Intervals1 Equation 22.4. Watchdog Timer Offset in PCA ClocksWatchdog Timer Usage PCA0CPL4SFR Definition 22.1. PCA0CN PCA Control Register Descriptions for PCACCF4 CCF3 CCF2 CCF1 CCF0 Cidl Wdte Wdlck CPS2 CPS1 CPS0 ECF SFR Definition 22.2. PCA0MD PCA ModeSFR Definition 22.3. PCA0CPMn PCA Capture/Compare Mode SFR Definition 22.5. PCA0H PCA Counter/Timer High Byte SFR Definition 22.4. PCA0L PCA Counter/Timer Low ByteSFR Definition 22.6. PCA0CPLn PCA Capture Module Low Byte SFR Definition 22.7. PCA0CPHn PCA Capture Module High Byte 23.1. C2 Interface Registers 23. C2 InterfaceC2 Register Definition 23.1. C2ADD C2 Address C2 Register Definition 23.2. Deviceid C2 Device IDC2 Register Definition 23.3. Revid C2 Revision ID Code CommandTypical C2 Pin Sharing 23.2. C2 Pin SharingContact Information