Silicon Laboratories C8051F346 SFR Definition 13.2. EMI0CF External Memory Configuration

C8051F340/1/2/3/4/5/6/7

SFR Definition 13.2. EMI0CF: External Memory Configuration

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

-

USBFAE

-

EMD2

EMD1

EMD0

EALE1

EALE0

00000011

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address: 0x85

Bit7:	Unused. Read = 0b. Write = don’t care.
Bit6:	USBFAE: USB FIFO Access Enable.
	0: USB FIFO RAM not available through MOVX instructions.
	1: USB FIFO RAM available using MOVX instructions. The 1k of USB RAM will be mapped
	in XRAM space at addresses 0x0400 to 0x07FF. The USB clock must be active to access
	this area with MOVX instructions.
Bit5:	Unused. Read = 0b. Write = don’t care.
Bit4:	EMD2: EMIF Multiplex Mode Select.

0:EMIF operates in multiplexed address/data mode.

1:EMIF operates in non-multiplexed mode (separate address and data pins).

Bits3–2: EMD1–0: EMIF Operating Mode Select.

These bits control the operating mode of the External Memory Interface.

00:Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to on-chip memory space.

01:Split Mode without Bank Select: Accesses below the 8k boundary are directed on-chip. Accesses above the 8k boundary are directed off-chip. 8-bit off-chip MOVX operations use the current contents of the Address High port latches to resolve upper address byte. Note that in order to access off-chip space, EMI0CN must be set to a page that is not contained in the on-chip address space.

10:Split Mode with Bank Select: Accesses below the 8k boundary are directed on-chip. Accesses above the 8k boundary are directed off-chip. 8-bit off-chip MOVX operations use the contents of EMI0CN to determine the high-byte of the address.

11:External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to the CPU.

Bits1–0: EALE1–0: ALE Pulse-Width Select Bits (only has effect when EMD2 = 0).

00:ALE high and ALE low pulse width = 1 SYSCLK cycle.

01:ALE high and ALE low pulse width = 2 SYSCLK cycles.

10:ALE high and ALE low pulse width = 3 SYSCLK cycles.

11:ALE high and ALE low pulse width = 4 SYSCLK cycles.

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