PCA Capture Mode Diagram | Silicon Laboratories C8051F341 instruction

C8051F340/1/2/3/4/5/6/7

22.2.1. Edge-triggered Capture Mode

In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/ timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused the capture.

PCA0CPMn

PCA Interrupt

Port I/O Crossbar

CEXn

PE C C M T P E W C A A A O W C M O P P T G M C 1 M P N n n n F

6	n n n				n
n
x 0				0 0 0 x

0

1

0

1

PCA0CN

C C C C C C C F R C C C C C F F F F F 4 3 2 1 0

CCFn)(to

PCA0CPLn PCA0CPHn

Capture

	PCA	PCA0L	PCA0H
	Timebase

Figure 22.4. PCA Capture Mode Diagram

Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware.

266

Rev. 0.5

Image 266

Silicon Laboratories C8051F341, C8051F347, C8051F346, C8051F343 PCA Capture Mode Diagram, Edge-triggered Capture Mode

Contents

HIGH-SPEED Controller Core Full Speed USB Flash MCU FamilyPrecision Internal Oscillators Rev Table Of Contents External Data Memory Interface and On-Chip Xram 117 Prefetch Engine Reset Sources 101Flash Memory 109 Universal Serial Bus Controller USB0 163 Oscillators 135Port Input/Output 147 SMBus 193 UART1 C8051F340/1/4/5 Only 219 Timers 243UART0 211 Enhanced Serial Peripheral Interface SPI0 229 Contact Information 282 Programmable Counter Array PCA0 26323. C2 Interface 279 C8051F340/1/2/3/4/5/6/7 Voltage Reference List of Figures and TablesAbsolute Maximum Ratings External Data Memory Interface and On-Chip Xram Prefetch Engine Reset SourcesFlash Memory Oscillators UART1 C8051F340/1/4/5 Only SMBusUART0 Enhanced Serial Peripheral Interface SPI0 23.C2 Interface TimersProgrammable Counter Array PCA0 List of Registers C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 System Overview TQFP48 Product Selection GuideRAM LQFP32 C8051F340/1/4/5 Block Diagram C8051F342/3/6/7 Block Diagram Fully 8051 Compatible Additional FeaturesCIP-51 Microcontroller Core Improved Throughput On-Chip Clock and Reset On-Chip Memory On-Chip Memory Map for 64kB Devices C8051F340/2/4/6 USB Controller Block Diagram Universal Serial Bus Controller Voltage Regulator On-Chip Debug Circuitry Digital Crossbar Diagram Programmable Digital I/O and Crossbar Serial Ports Programmable Counter Array Bit ADC Block Diagram Bit Analog to Digital Converter 10. Comparator0 Block Diagram GND Absolute Maximum RatingsParameter Conditions Min Typ Max Units Global DC Electrical Characteristics TBD Index to Electrical Characteristics Tables Table Title Name Pin Numbers Type Description 48-pin 32-pin Pinout and Package DefinitionsPin Definitions for the C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 C8051F340/1/4/5 Top View MIN TYP MAX Package DimensionsTQFP-48 LQFP-32 Pinout Diagram Top View GND VDD Regin Vbus LQFP-32 Package Diagram LQFP-32 C8051F340/1/2/3/4/5/6/7 ADC0 Functional Block Diagram Bit ADC ADC0 Analog Multiplexer Vref Temperature Sensor Temperature Sensor Transfer Function Temperature degrees C Modes of Operation Starting a Conversion Bit ADC Track and Conversion Example Timing Tracking Modes Settling Time Requirements Differential Mode Single-Ended ModeEquation 5.1. ADC0 Settling Time Requirements AMX0P4-0 ADC0 Positive Input Pin Package SFR Definition 5.1. AMX0P AMUX0 Positive Channel SelectAMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 Reserved AMX0N4-0 ADC0 Negative Input Pin Package SFR Definition 5.2. AMX0N AMUX0 Negative Channel SelectAMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 SFR Definition 5.5. ADC0L ADC0 Data Word LSB SFR Definition 5.3. ADC0CF ADC0 ConfigurationSFR Definition 5.4. ADC0H ADC0 Data Word MSB AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0LJST SFR Definition 5.6. ADC0CN ADC0 Control AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 Programmable Window Detector SFR Definition 5.8. ADC0GTL ADC0 Greater-Than Data Low Byte SFR Definition 5.9. ADC0LTH ADC0 Less-Than Data High Byte SFR Definition 5.10. ADC0LTL ADC0 Less-Than Data Low Byte Window Detector In Single-Ended Mode ADC Window Compare Example Right-Justified Single-Ended Data Window Detector In Differential Mode ADC Window Compare Example Right-Justified Differential Data Analog Inputs ADC0 Electrical CharacteristicsConversion Rate Voltage Reference Functional Block Diagram Voltage Reference Refsl Tempe Biase Refbe Voltage Reference Electrical CharacteristicsSFR Definition 6.1. REF0CN Reference Control External Reference Refbe = Comparators Comparator Functional Block Diagram Comparator Hysteresis Plot SFR Definition 7.1. CPT0CN Comparator0 Control CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 Negative Input Pin Package SFR Definition 7.2. CPT0MX Comparator0 MUX SelectionCMX0N1 CMX0N0 CMX0P1 CMX0P0 Mode SFR Definition 7.3. CPT0MD Comparator0 Mode SelectionCP0RIE CP0FIE CP0MD1 CP0MD0 CP0MD1 CP0MD0 SFR Definition 7.4. CPT1CN Comparator1 Control CP1EN CP1OUT CP1RIF CP1FIF CMX1N2 CMX1N1 CMX1N0 SFR Definition 7.5. CPT1MX Comparator1 MUX SelectionCMX1N2 CMX1N1 CMX1N0 CMX1P2 CMX1P1 CMX1P0 CMX1P2 CMX1P1 CMX1P0 CP1MD1 CP1MD0 SFR Definition 7.6. CPT1MD Comparator1 Mode SelectionCP1RIE CP1FIE CP1MD1 CP1MD0 CP1 Response Time Comparator Electrical Characteristics Voltage Regulator REG0 Regulator Mode SelectionVoltage Regulator Electrical Specifications Vbus Detection REG0 Configuration USB Bus-Powered REG0 Configuration USB Self-Powered, Regulator Disabled SFR Definition 8.1. REG0CN Voltage Regulator Control Regdis Vbstat Vbpol Regmod CIP-51 Block Diagram CIP-51 Microcontroller Performance Instruction SetInstruction and CPU Timing Logical Operations CIP-51 Instruction Set SummaryMovx Instruction and Program Memory Mnemonic Description Bytes Clock Cycles Data Transfer Boolean Manipulation Program Branching C8051F340/1/2/3/4/5/6/7 Memory Organization Program Memory Bit Addressable Locations Data MemoryGeneral Purpose Registers Stack Special Function Register SFR Memory Map Special Function Registers ADC0L Special Function RegistersRegister Address Description PSW REF0CN SPI0CN SFR Definition 9.3. SP Stack Pointer SFR Definition 9.1. DPL Data Pointer Low ByteSFR Definition 9.2. DPH Data Pointer High Byte Register Descriptions RS1 RS0 SFR Definition 9.4. PSW Program Status WordSFR Definition 9.5. ACC Accumulator Register Bank Address MCU Interrupt Sources and Vectors SFR Definition 9.6. B B RegisterInterrupt Handler External Interrupts IT0 IN0PL Interrupt PrioritiesInterrupt Latency IT1 IN1PL Interrupt Summary Interrupt Register Descriptions SFR Definition 9.7. IE Interrupt Enable ESPI0 ET2 ES0 ET1 EX1 ET0 EX0 SFR Definition 9.8. IP Interrupt Priority PSPI0 PT2 PS0 PT1 PX1 PT0 PX0 SFR Definition 9.9. EIE1 Extended Interrupt Enable ET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 EUSB0 ESMB0 SFR Definition 9.10. EIP1 Extended Interrupt Priority PT3 PCP1 PCP0 PPCA0 PADC0 PWADC0 PUSB0 PSMB0 ES1 Evbus SFR Definition 9.11. EIE2 Extended Interrupt EnableSFR Definition 9.12. EIP2 Extended Interrupt Priority PS1 Pvbus IN1SL2-0 INT1 Port Pin SFR Definition 9.13. IT01CF INT0/INT1 ConfigurationIN1PL IN1SL2 IN1SL1 IN1SL0 IN0PL IN0SL2 IN0SL1 IN0SL0 IN0SL2-0 INT0 Port Pin Stop Mode Power Management ModesIdle Mode SFR Definition 9.14. Pcon Power Control GF5 GF4 GF3 GF2 GF1 GF0 Stop Idle C8051F340/1/2/3/4/5/6/7 Pfen Flbwe Prefetch EngineSFR Definition 10.1. PFE0CN Prefetch Engine Control 100 Reset Sources Power-On Reset Power-On and VDD Monitor Reset Timing Vdmen Power-Fail Reset / VDD MonitorSFR Definition 11.1. VDM0CN VDD Monitor Control Comparator0 Reset External ResetMissing Clock Detector Reset PCA Watchdog Timer Reset Software Reset USB Reset SFR Definition 11.2. Rstsrc Reset Source Usbrsf Ferror C0RSEF Swrsf Wdtrsf Mcdrsf Porsf Pinrsf Reset Electrical Characteristics 108 Programming The Flash Memory Flash Erase ProcedureFlash Memory Flash Lock and Key Functions Flash Write Procedure Security Options Flash Electrical CharacteristicsNon-volatile Data Storage Flash Program Memory Map and Security Byte Accessing Flash from the C2 debug interface Pswe SFR Definition 12.1. Psctl Program Store R/W ControlSFR Definition 12.2. Flkey Flash Lock and Key Flrt SFR Definition 12.3. Flscl Flash ScaleFose 116 Bit Movx Example Accessing XramExternal Data Memory Interface and On-Chip Xram Accessing USB Fifo Space USB Fifo Space Configuring the External Memory Interface Port Configuration PGSEL7 PGSEL6 PGSEL5 PGSEL4 PGSEL3 PGSEL2 PGSEL1 PGSEL0 SFR Definition 13.2. EMI0CF External Memory Configuration Usbfae EMD2 EMD1 EMD0 EALE1 EALE0 Multiplexed Configuration Multiplexed and Non-multiplexed Selection Non-multiplexed Configuration Example Memory Mode Selection Non-multiplexed Configuration Split Mode without Bank Select Internal Xram Only External Only Split Mode with Bank SelectTiming SFR Definition 13.3. EMI0TC External Memory Timing Control EAS1 EAS0 ERW3 EWR2 EWR1 EWR0 EAH1 EAH0 Emif Write Data Non-multiplexed ModeBit Movx EMI0CF42 = ‘101’, ‘110’, or ‘111’ Emif Read Data Non-multiplexed 8-bit Movx without Bank Select Timing Bit Movx without Bank Select EMI0CF42 = ‘101’ or ‘111’ Non-multiplexed 8-bit Movx with Bank Select Timing Bit Movx with Bank Select EMI0CF42 = ‘110’ Multiplexed Mode Bit Movx EMI0CF42 = ‘001’, ‘010’, or ‘011’ Multiplexed 8-bit Movx without Bank Select Timing Bit Movx without Bank Select EMI0CF42 = ‘001’ or ‘011’ 10. Multiplexed 8-bit Movx with Bank Select Timing Bit Movx with Bank Select EMI0CF42 = ‘010’ AC Parameters for External Memory Interface Parameter Description Min Max Units 134 Oscillator Diagram Oscillators SFR Definition 14.1. Oscicn Internal H-F Oscillator Control Internal H-F Oscillator Suspend ModeProgrammable Internal High-Frequency H-F Oscillator Ioscen Ifrdy Suspend IFCN1 IFCN0 Osccal Programmable Internal Low-Frequency L-F OscillatorCalibrating the Internal L-F Oscillator SFR Definition 14.3. Osclcn Internal L-F Oscillator Control Osclen Osclrdy OSCLF3 OSCLF2 OSCLF1 OSCLF0 OSCLD1 OSCLD0 External Crystal Example Clocking Timers Directly Through the External OscillatorExternal Oscillator Drive Circuit External RC Example External Capacitor Example Xfcn SFR Definition 14.4. Oscxcn External Oscillator ControlXtlvld XOSCMD2 XOSCMD1 XOSCMD0 XFCN2 XFCN1 XFCN0 Mulen Mulinit Mulrdy Mulsel Clock MultiplierSFR Definition 14.5. Clkmul Clock Multiplier Control Mulsel System and USB Clock Selection External Oscillator Clock SignalInternal Oscillator Clock Signal System Clock Selection Usbclk SFR Definition 14.6. Clksel Clock SelectUsbclk Clksl Clksl Oscillator Electrical Characteristics External USB Clock Requirements 146 Port I/O Functional Block Diagram Port 0 through Port Port Input/Output Port I/O Cell Block Diagram Crossbar Priority Decoder with No Pins Skipped Priority Crossbar Decoder Crossbar Priority Decoder with Crystal Pins Skipped Port I/O Initialization SFR Definition 15.1. XBR0 Port I/O Crossbar Register CP1AE CP1E CP0AE CP0E Syscke SMB0E SPI0E URT0E Weakpud Xbare T1E T0E Ecie PCA0ME SFR Definition 15.2. XBR1 Port I/O Crossbar RegisterSFR Definition 15.3. XBR2 Port I/O Crossbar Register URT1E SFR Definition 15.4. P0 Port0 Latch SFR Definition 15.5. P0MDIN Port0 Input ModeGeneral Purpose Port I/O SFR Definition 15.6. P0MDOUT Port0 Output Mode SFR Definition 15.7. P0SKIP Port0 Skip SFR Definition 15.8. P1 Port1 Latch SFR Definition 15.9. P1MDIN Port1 Input ModeSFR Definition 15.10. P1MDOUT Port1 Output Mode SFR Definition 15.12. P2 Port2 Latch SFR Definition 15.13. P2MDIN Port2 Input ModeSFR Definition 15.11. P1SKIP Port1 Skip SFR Definition 15.14. P2MDOUT Port2 Output Mode SFR Definition 15.15. P2SKIP Port2 Skip SFR Definition 15.16. P3 Port3 Latch SFR Definition 15.17. P3MDIN Port3 Input ModeSFR Definition 15.18. P3MDOUT Port3 Output Mode SFR Definition 15.19. P3SKIP Port3 Skip SFR Definition 15.20. P4 Port4 Latch SFR Definition 15.21. P4MDIN Port4 Input Mode SFR Definition 15.22. P4MDOUT Port4 Output Mode Port I/O DC Electrical Characteristics USB0 Block Diagram Universal Serial Bus Controller USB0 USB Transceiver Endpoint AddressingEndpoint Addressing Scheme Endpoint Associated Pipes USB Protocol Address PHYTST10 SFR Definition 16.1. USB0XCN USB0 Transceiver ControlPren Phyen Speed PHYTST1 PHYTST0 Dfrec USB Register Access USB0 Register Access Scheme SFR Definition 16.2. USB0ADR USB0 Indirect Address Busy Autord Usbaddr SFR Definition 16.3. USB0DAT USB0 Data Index USB0 Controller RegistersUSB Register Definition 16.4. Index USB0 Endpoint Index Communication Speed USB Clock 4x Clock Multiplier Input USB Clock ConfigurationUSB Register Definition 16.5. Clkrec Clock Recovery Control CRE Crssen Crlow Fifo Split Mode Fifo Management Fifo Double Buffering Fifo ConfigurationsFifo Access Fifodata USB Register Definition 16.7. Faddr USB0 Function Address Function Configuration and ControlFunction Addressing 174 USB Register Definition 16.8. Power USB0 Power Isoud Usbinh Usbrst Resume Susmd Susen USB Register Definition 16.9. Framel USB0 Frame Number Low Interrupts IN3 IN2 IN1 EP0 OUT3 OUT2 OUT1 USB Register Definition 16.13. Cmint USB0 Common Interrupt SOF Rstint Rsuint Susint IN3E IN2E IN1E EP0E OUT3E OUT2E OUT1E Sofe Rstinte Rsuinte Susinte Serial Interface EngineEndpoint0 Endpoint0 Setup Transactions Endpoint0 in Transactions Endpoint0 OUT Transactions Ssuend USB Register Definition 16.17. E0CSR USB0 Endpoint0 ControlSsuend Soprdy Sdstl Suend Dataend Ststl Inprdy Oprdy Controlling Endpoints1-3 Configuring Endpoints1-3Endpoints1-3 in Interrupt or Bulk Mode Endpoints1-3 in Isochronous Mode Clrdt Ststl Sdstl Flush Undrun Fifone Inprdy A packet being transmitted Dbien ISO Dirsel Fcdt Split Endpoints1-3 OUT Interrupt or Bulk ModeControlling Endpoints1-3 OUT Endpoints1-3 OUT Isochronous Mode Clrdt Ststl Sdstl Flush Daterr Ovrun Fifoful Oprdy E0CH Dboen ISOEocl USB Transceiver Electrical Characteristics Receiver 192 SMBus Block Diagram SMBus SMBus Configuration Supporting Documents SMBus Transaction Arbitration SCL High SMBus Free Timeout Using the SMBusSCL Low Timeout Clock Low Extension Tion Register on Equation 17.1. Minimum SCL High and Low Times SMBus Configuration RegisterSMBus Clock Source Selection Equation 17.2. Typical SMBus Bit Rate Exthold Minimum SDA Setup and Hold TimesMinimum SDA Setup Time Minimum SDA Hold Time SFR Definition 17.1. SMB0CF SMBus Clock/Configuration Ensmb INH Busy Exthold Smbtoe Smbfte SMBCS1 SMBCS0 SMB0CN Control Register SFR Definition 17.2. SMB0CN SMBus Control Master Txmode STA STO Ackrq Arblost ACK Bit Set by Hardware When Cleared by Hardware When Sources for Hardware Changes to SMB0CN SMBus Transfer Modes Master Transmitter ModeSFR Definition 17.3. SMB0DAT SMBus Data Data Register Typical Master Transmitter Sequence Master Receiver Mode Typical Master Receiver Sequence Slave Receiver Mode Typical Slave Receiver Sequence Slave Transmitter Mode Typical Slave Transmitter Sequence SMBus Status Decoding Start Values ReadCurrent SMbus State Typical Response Options Slave byte was transmitted No action required expect UART0 Block Diagram UART0 Operational Modes Enhanced Baud Rate GenerationEquation 18.1. UART0 Baud Rate Uart Interconnect Diagram Bit Uart Bit Uart Timing Diagram Multiprocessor Communications Master Slave Device TI0 RI0 SFR Definition 18.1. SCON0 Serial Port 0 ControlS0MODE MCE0 REN0 SFR Definition 18.2. SBUF0 Serial UART0 Port Data Buffer SCA1-SCA0 Target Actual Baud Oscillator Timer ClockT1M Timer Baud Rate Error Divide Source Pre-scale Rate bps Factor Select UART1 Block Diagram UART1 C8051F340/1/4/5 Only Equation 19.1. UART1 Baud Rate Baud Rate Generator Settings for Standard Baud RatesBaud Rate Generator SBRLH1SBRLL1 Data Format UART1 Timing Without Parity or Extra Bit Data Reception Configuration and OperationData Transmission Multiprocessor Communications Fifo SFR Definition 19.1. SCON1 UART1 ControlOVR1 PERR1 THRE1 REN1 TBX1 RBX1 TI1 RI1 SFR Definition 19.2. SMOD1 UART1 Mode MCE1 S1PT1 S1PT0 PE1 S1DL1 S1DL0 XBE1 SBL1 SB1PS1 SB1PS0 SFR Definition 19.3. SBUF1 UART1 Data BufferSB1RUN Rev 227 228 SPI Block Diagram Enhanced Serial Peripheral Interface SPI0 Master In, Slave Out Miso Signal DescriptionsMaster Out, Slave In Mosi Serial Clock SCK SPI0 Master Mode Operation Multiple-Master Mode Connection Diagram SPI0 Slave Mode Operation SPI0 Interrupt Sources Master Mode Data/Clock Timing Serial Clock Timing Slave Mode Data/Clock Timing Ckpha = Spibsy Msten Ckpha Ckpol Slvsel Nssin Srmt Rxbmt SFR Definition 20.1. SPI0CFG SPI0 ConfigurationSPI Special Function Registers SFR Definition 20.2. SPI0CN SPI0 Control Spif Wcol Modf Rxovrn NSSMD1 NSSMD0 Txbmt Spien SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SFR Definition 20.3. SPI0CKR SPI0 Clock RateSFR Definition 20.4. SPI0DAT SPI0 Data SPI Master Timing Ckpha = 10. SPI Slave Timing Ckpha = Only Slave Mode Timing* See FigureSPI Slave Timing Parameters 242 Mode 0 13-bit Counter/Timer TimersTimer 0 and Timer Timer 0 and Timer 1 Modes Timer 2 Modes Timer 3 Modes TR0 GATE0 INT0 Mode 1 16-bit Counter/TimerCounter/Timer T0 Mode 2 Block Diagram Mode 2 8-bit Counter/Timer with Auto-Reload T0 Mode 3 Block Diagram Mode 3 Two 8-bit Counter/Timers Timer 0 Only SFR Definition 21.1. Tcon Timer Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 GATE0 SFR Definition 21.2. Tmod Timer ModeGATE1 T1M1 T1M0 SCA1 SCA0 SFR Definition 21.3. Ckcon Clock ControlT3MH T3ML T2MH T2ML T1M T0M SCA1 SCA0 Prescaled Clock SFR Definition 21.6. TH0 Timer 0 High Byte SFR Definition 21.4. TL0 Timer 0 Low ByteSFR Definition 21.5. TL1 Timer 1 Low Byte SFR Definition 21.7. TH1 Timer 1 High Byte Timer Bit Timer with Auto-Reload TMR2H Clock Source Bit Timers with Auto-ReloadT2MH T2XCLK T2ML T2XCLK Timer 2 Capture Mode T2SPLIT = ‘0’ Timer 2 Capture Mode T2SPLIT = ‘1’ SFR Definition 21.8. TMR2CN Timer 2 Control TF2H TF2L TF2LEN T2CE T2SPLIT TR2 T2CSS T2XCLK SFR Definition 21.11. TMR2L Timer 2 Low Byte SFR Definition 21.12. TMR2H Timer 2 High Byte Timer 3 16-Bit Mode Block Diagram T3ML T3XCLK T3MH T3XCLKTMR3H Clock Source TMR3L Clock Source 10. Timer 3 Capture Mode T3SPLIT = ‘0’ USB Start-of-Frame Capture 11. Timer 3 Capture Mode T3SPLIT = ‘1’ SFR Definition 21.13. TMR3CN Timer 3 Control TF3H TF3L TF3LEN T3CE T3SPLIT TR3 T3CSS T3XCLK SFR Definition 21.16. TMR3L Timer 3 Low Byte SFR Definition 21.17. TMR3H Timer 3 High Byte Programmable Counter Array PCA0 CPS2 CPS1 CPS0 PCA Counter/TimerPCA Timebase Input Options Timebase Capture/Compare Modules PCA0CPM Register Settings for PCA Capture/Compare ModulesOperation Mode PWM16 Ecom Capp Capn MAT TOG Eccf PCA Capture Mode Diagram Edge-triggered Capture Mode PCA Software Timer Mode Diagram Software Timer Compare Mode PCA High Speed Output Mode Diagram High Speed Output Mode Frequency Output Mode Equation 22.1. Square Wave Frequency Output Bit Pulse Width Modulator Mode Equation 22.2 -Bit PWM Duty Cycle PCA 16-Bit PWM Mode Equation 22.3 -Bit PWM Duty Cycle Watchdog Timer Mode Watchdog Timer Operation Watchdog Timer Usage Equation 22.4. Watchdog Timer Offset in PCA ClocksWatchdog Timer Timeout Intervals1 PCA0CPL4 CCF4 CCF3 CCF2 CCF1 CCF0 Register Descriptions for PCASFR Definition 22.1. PCA0CN PCA Control SFR Definition 22.2. PCA0MD PCA Mode Cidl Wdte Wdlck CPS2 CPS1 CPS0 ECF SFR Definition 22.3. PCA0CPMn PCA Capture/Compare Mode SFR Definition 22.6. PCA0CPLn PCA Capture Module Low Byte SFR Definition 22.4. PCA0L PCA Counter/Timer Low ByteSFR Definition 22.5. PCA0H PCA Counter/Timer High Byte SFR Definition 22.7. PCA0CPHn PCA Capture Module High Byte C2 Register Definition 23.1. C2ADD C2 Address 23. C2 Interface23.1. C2 Interface Registers C2 Register Definition 23.2. Deviceid C2 Device ID Code Command C2 Register Definition 23.3. Revid C2 Revision ID 23.2. C2 Pin Sharing Typical C2 Pin Sharing Contact Information