Silicon Laboratories C8051F341, C8051F347, C8051F346 SFR Definition 17.2. SMB0CN SMBus Control

C8051F340/1/2/3/4/5/6/7

SFR Definition 17.2. SMB0CN: SMBus Control

R R R/W R/W R R R/W R/W Reset Value

MASTER TXMODE

STA

STO

ACKRQ ARBLOST

ACK

SI

00000000

Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0	Bit
								Addressable
						SFR Address: 0xC0
Bit7:	MASTER: SMBus Master/Slave Indicator.
	This read-only bit indicates when the SMBus is operating as a master.
	0: SMBus operating in Slave Mode.
	1: SMBus operating in Master Mode.
Bit6:	TXMODE: SMBus Transmit Mode Indicator.
	This read-only bit indicates when the SMBus is operating as a transmitter.
	0: SMBus in Receiver Mode.
	1: SMBus in Transmitter Mode.
Bit5:	STA: SMBus Start Flag.
	Write:
	0: No Start generated.
	1: When operating as a master, a START condition is transmitted if the bus is free (If the bus
	is not free, the START is transmitted after a STOP is received or a timeout is detected). If
	STA is set by software as an active Master, a repeated START will be generated after the
	next ACK cycle.
	Read:
	0: No Start or repeated Start detected.
	1: Start or repeated Start detected.
Bit4:	STO: SMBus Stop Flag.
	Write:
	0: No STOP condition is transmitted.
	1: Setting STO to logic 1 causes a STOP condition to be transmitted after the next ACK
	cycle. When the STOP condition is generated, hardware clears STO to logic 0. If both STA
	and STO are set, a STOP condition is transmitted followed by a START condition.
	Read:
	0: No Stop condition detected.
	1: Stop condition detected (if in Slave Mode) or pending (if in Master Mode).
Bit3:	ACKRQ: SMBus Acknowledge Request
	This read-only bit is set to logic 1 when the SMBus has received a byte and needs the ACK
	bit to be written with the correct ACK response value.
Bit2:	ARBLOST: SMBus Arbitration Lost Indicator.
	This read-only bit is set to logic 1 when the SMBus loses arbitration while operating as a
	transmitter. A lost arbitration while a slave indicates a bus error condition.
Bit1:	ACK: SMBus Acknowledge Flag.
	This bit defines the out-going ACK level and records incoming ACK levels. It should be writ-
	ten each time a byte is received (when ACKRQ=1), or read after each byte is transmitted.
	0: A "not acknowledge" has been received (if in Transmitter Mode) OR will be transmitted (if
	in Receiver Mode).
	1: An "acknowledge" has been received (if in Transmitter Mode) OR will be transmitted (if in
	Receiver Mode).
Bit0:	SI: SMBus Interrupt Flag.
	This bit is set by hardware under the conditions listed in Table 17.3. SI must be cleared by
	software. While SI is set, SCL is held low and the SMBus is stalled.

202 Rev. 0.5