Silicon Laboratories C8051F343, C8051F347, C8051F346, C8051F341 Fifo Management, Fifo Split Mode

C8051F340/1/2/3/4/5/6/7

16.5. FIFO Management

1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between Endpoints0-3 as shown in Figure 16.3. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT, or both (Split Mode: half IN, half OUT).

0x07FF	Endpoint0
0x07C0	(64 bytes)
0x07BF	Endpoint1
0x0740	(128 bytes)
0x073F
	Endpoint2	Configurable as
	(256 bytes)	IN, OUT, or both (Split
0x0640		Mode)
0x063F

Endpoint3 (512 bytes)

0x0440

0x043F

Free

(64 bytes)

0x0400

USB Clock Domain

System Clock Domain

0x03FF

User XRAM (1024 bytes)

0x0000

Figure 16.3. USB FIFO Allocation

16.5.1. FIFO Split Mode

The FIFO space for Endpoints1-3 can be split such that the upper half of the FIFO space is used by the IN endpoint, and the lower half is used by the OUT endpoint. For example: if the Endpoint3 FIFO is configured for Split Mode, the upper 256 bytes (0x0540 to 0x063F) are used by Endpoint3 IN and the lower 256 bytes (0x0440 to 0x053F) are used by Endpoint3 OUT.

If an endpoint FIFO is not configured for Split Mode, that endpoint IN/OUT pair’s FIFOs are combined to form a single IN or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at a time. The endpoint direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint’s EINCSRH register (see SFR Definition 16.20).

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