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Silicon Laboratories C8051F347 C2 Register Definition 23.3. Revid C2 Revision ID, Code Command

Models: C8051F346 C8051F347 C8051F344 C8051F342 C8051F343 C8051F345 C8051F340 C8051F341

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C8051F340/1/2/3/4/5/6/7

C2 Register Definition 23.3. REVID: C2 Revision ID

Reset Value

Variable

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

This read-only register returns the 8-bit revision ID.

C2 Register Definition 23.4. FPCTL: C2 Flash Programming Control

Reset Value 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bits7–0 FPCTL: Flash Programming Control Register.

This register is used to enable Flash programming via the C2 interface. To enable C2 Flash programming, the following codes must be written in order: 0x02, 0x01. Note that once C2 Flash programming is enabled, a system reset must be issued to resume normal operation.

C2 Register Definition 23.5. FPDAT: C2 Flash Programming Data

Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bits7–0: FPDAT: C2 Flash Programming Data Register.

This register is used to pass Flash commands, addresses, and data during C2 Flash accesses. Valid commands are listed below.

Code	Command
0x06	Flash Block Read
0x07	Flash Block Write
0x08	Flash Page Erase
0x03	Device Erase

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Rev. 0.5

Image 280

Silicon Laboratories C8051F347, C8051F346, C8051F341 C2 Register Definition 23.3. Revid C2 Revision ID, Code Command

Contents

Precision Internal Oscillators Full Speed USB Flash MCU FamilyHIGH-SPEED Controller Core Rev Table Of Contents Flash Memory 109 Prefetch Engine Reset Sources 101External Data Memory Interface and On-Chip Xram 117 Oscillators 135 Port Input/Output 147Universal Serial Bus Controller USB0 163 SMBus 193Timers 243 UART0 211UART1 C8051F340/1/4/5 Only 219 Enhanced Serial Peripheral Interface SPI0 22923. C2 Interface 279 Programmable Counter Array PCA0 263Contact Information 282 C8051F340/1/2/3/4/5/6/7 Absolute Maximum Ratings List of Figures and TablesVoltage Reference Prefetch Engine Reset Sources Flash MemoryExternal Data Memory Interface and On-Chip Xram OscillatorsSMBus UART0UART1 C8051F340/1/4/5 Only Enhanced Serial Peripheral Interface SPI0Programmable Counter Array PCA0 Timers23.C2 Interface List of Registers C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 System Overview Product Selection Guide RAMTQFP48 LQFP32C8051F340/1/4/5 Block Diagram C8051F342/3/6/7 Block Diagram Additional Features CIP-51 Microcontroller CoreFully 8051 Compatible Improved ThroughputOn-Chip Clock and Reset On-Chip Memory On-Chip Memory Map for 64kB Devices C8051F340/2/4/6USB Controller Block Diagram Universal Serial Bus ControllerVoltage Regulator On-Chip Debug CircuitryDigital Crossbar Diagram Programmable Digital I/O and CrossbarSerial Ports Programmable Counter ArrayBit ADC Block Diagram Bit Analog to Digital Converter10. Comparator0 Block Diagram Parameter Conditions Min Typ Max Units Absolute Maximum RatingsGND Global DC Electrical Characteristics TBDIndex to Electrical Characteristics Tables Table Title Pin Definitions for the C8051F340/1/2/3/4/5/6/7 Pinout and Package DefinitionsName Pin Numbers Type Description 48-pin 32-pin C8051F340/1/2/3/4/5/6/7 C8051F340/1/2/3/4/5/6/7 C8051F340/1/4/5 Top View TQFP-48 Package DimensionsMIN TYP MAX LQFP-32 Pinout Diagram Top View GND VDD Regin VbusLQFP-32 Package Diagram LQFP-32C8051F340/1/2/3/4/5/6/7 ADC0 Functional Block Diagram Bit ADC ADC0Analog Multiplexer VrefTemperature Sensor Temperature Sensor Transfer FunctionTemperature degrees C Modes of Operation Starting a ConversionBit ADC Track and Conversion Example Timing Tracking ModesEquation 5.1. ADC0 Settling Time Requirements Differential Mode Single-Ended ModeSettling Time Requirements SFR Definition 5.1. AMX0P AMUX0 Positive Channel Select AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0AMX0P4-0 ADC0 Positive Input Pin Package ReservedAMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 SFR Definition 5.2. AMX0N AMUX0 Negative Channel SelectAMX0N4-0 ADC0 Negative Input Pin Package SFR Definition 5.3. ADC0CF ADC0 Configuration SFR Definition 5.4. ADC0H ADC0 Data Word MSBSFR Definition 5.5. ADC0L ADC0 Data Word LSB AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0LJSTSFR Definition 5.6. ADC0CN ADC0 Control AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0Programmable Window Detector SFR Definition 5.8. ADC0GTL ADC0 Greater-Than Data Low ByteSFR Definition 5.9. ADC0LTH ADC0 Less-Than Data High Byte SFR Definition 5.10. ADC0LTL ADC0 Less-Than Data Low ByteWindow Detector In Single-Ended Mode ADC Window Compare Example Right-Justified Single-Ended DataWindow Detector In Differential Mode ADC Window Compare Example Right-Justified Differential DataConversion Rate ADC0 Electrical CharacteristicsAnalog Inputs Voltage Reference Functional Block Diagram Voltage ReferenceVoltage Reference Electrical Characteristics SFR Definition 6.1. REF0CN Reference ControlRefsl Tempe Biase Refbe External Reference Refbe =Comparators Comparator Functional Block Diagram Comparator Hysteresis Plot SFR Definition 7.1. CPT0CN Comparator0 Control CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0SFR Definition 7.2. CPT0MX Comparator0 MUX Selection CMX0N1 CMX0N0Negative Input Pin Package CMX0P1 CMX0P0SFR Definition 7.3. CPT0MD Comparator0 Mode Selection CP0RIE CP0FIE CP0MD1 CP0MD0Mode CP0MD1 CP0MD0SFR Definition 7.4. CPT1CN Comparator1 Control CP1EN CP1OUT CP1RIF CP1FIFSFR Definition 7.5. CPT1MX Comparator1 MUX Selection CMX1N2 CMX1N1 CMX1N0 CMX1P2 CMX1P1 CMX1P0CMX1N2 CMX1N1 CMX1N0 CMX1P2 CMX1P1 CMX1P0SFR Definition 7.6. CPT1MD Comparator1 Mode Selection CP1RIE CP1FIE CP1MD1 CP1MD0CP1MD1 CP1MD0 CP1 Response TimeComparator Electrical Characteristics Regulator Mode Selection Voltage Regulator Electrical SpecificationsVoltage Regulator REG0 Vbus DetectionREG0 Configuration USB Bus-Powered REG0 Configuration USB Self-Powered, Regulator Disabled SFR Definition 8.1. REG0CN Voltage Regulator Control Regdis Vbstat Vbpol RegmodCIP-51 Block Diagram CIP-51 MicrocontrollerInstruction and CPU Timing Instruction SetPerformance Movx Instruction and Program Memory CIP-51 Instruction Set SummaryLogical Operations Mnemonic Description Bytes Clock Cycles Data TransferBoolean Manipulation Program BranchingC8051F340/1/2/3/4/5/6/7 Memory Organization Program MemoryData Memory General Purpose RegistersBit Addressable Locations StackSpecial Function Register SFR Memory Map Special Function RegistersRegister Address Description Special Function RegistersADC0L PSW REF0CNSPI0CN SFR Definition 9.1. DPL Data Pointer Low Byte SFR Definition 9.2. DPH Data Pointer High ByteSFR Definition 9.3. SP Stack Pointer Register DescriptionsSFR Definition 9.4. PSW Program Status Word SFR Definition 9.5. ACC AccumulatorRS1 RS0 Register Bank AddressSFR Definition 9.6. B B Register Interrupt HandlerMCU Interrupt Sources and Vectors External InterruptsInterrupt Priorities Interrupt LatencyIT0 IN0PL IT1 IN1PLInterrupt Summary Interrupt Register DescriptionsSFR Definition 9.7. IE Interrupt Enable ESPI0 ET2 ES0 ET1 EX1 ET0 EX0SFR Definition 9.8. IP Interrupt Priority PSPI0 PT2 PS0 PT1 PX1 PT0 PX0SFR Definition 9.9. EIE1 Extended Interrupt Enable ET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 EUSB0 ESMB0SFR Definition 9.10. EIP1 Extended Interrupt Priority PT3 PCP1 PCP0 PPCA0 PADC0 PWADC0 PUSB0 PSMB0SFR Definition 9.11. EIE2 Extended Interrupt Enable SFR Definition 9.12. EIP2 Extended Interrupt PriorityES1 Evbus PS1 PvbusSFR Definition 9.13. IT01CF INT0/INT1 Configuration IN1PL IN1SL2 IN1SL1 IN1SL0 IN0PL IN0SL2 IN0SL1 IN0SL0IN1SL2-0 INT1 Port Pin IN0SL2-0 INT0 Port PinIdle Mode Power Management ModesStop Mode SFR Definition 9.14. Pcon Power Control GF5 GF4 GF3 GF2 GF1 GF0 Stop IdleC8051F340/1/2/3/4/5/6/7 SFR Definition 10.1. PFE0CN Prefetch Engine Control Prefetch EnginePfen Flbwe 100 Reset Sources Power-On Reset Power-On and VDD Monitor Reset TimingSFR Definition 11.1. VDM0CN VDD Monitor Control Power-Fail Reset / VDD MonitorVdmen External Reset Missing Clock Detector ResetComparator0 Reset PCA Watchdog Timer ResetSoftware Reset USB ResetSFR Definition 11.2. Rstsrc Reset Source Usbrsf Ferror C0RSEF Swrsf Wdtrsf Mcdrsf Porsf PinrsfReset Electrical Characteristics 108 Flash Erase Procedure Flash MemoryProgramming The Flash Memory Flash Lock and Key FunctionsFlash Write Procedure Non-volatile Data Storage Flash Electrical CharacteristicsSecurity Options Flash Program Memory Map and Security Byte Accessing Flash from the C2 debug interface SFR Definition 12.2. Flkey Flash Lock and Key SFR Definition 12.1. Psctl Program Store R/W ControlPswe Fose SFR Definition 12.3. Flscl Flash ScaleFlrt 116 External Data Memory Interface and On-Chip Xram Accessing XramBit Movx Example Accessing USB Fifo Space USB Fifo SpaceConfiguring the External Memory Interface Port ConfigurationPGSEL7 PGSEL6 PGSEL5 PGSEL4 PGSEL3 PGSEL2 PGSEL1 PGSEL0 SFR Definition 13.2. EMI0CF External Memory Configuration Usbfae EMD2 EMD1 EMD0 EALE1 EALE0Multiplexed Configuration Multiplexed and Non-multiplexed SelectionNon-multiplexed Configuration Example Memory Mode Selection Non-multiplexed ConfigurationSplit Mode without Bank Select Internal Xram OnlyTiming Split Mode with Bank SelectExternal Only SFR Definition 13.3. EMI0TC External Memory Timing Control EAS1 EAS0 ERW3 EWR2 EWR1 EWR0 EAH1 EAH0Non-multiplexed Mode Bit Movx EMI0CF42 = ‘101’, ‘110’, or ‘111’Emif Write Data Emif Read DataNon-multiplexed 8-bit Movx without Bank Select Timing Bit Movx without Bank Select EMI0CF42 = ‘101’ or ‘111’Non-multiplexed 8-bit Movx with Bank Select Timing Bit Movx with Bank Select EMI0CF42 = ‘110’Multiplexed Mode Bit Movx EMI0CF42 = ‘001’, ‘010’, or ‘011’Multiplexed 8-bit Movx without Bank Select Timing Bit Movx without Bank Select EMI0CF42 = ‘001’ or ‘011’10. Multiplexed 8-bit Movx with Bank Select Timing Bit Movx with Bank Select EMI0CF42 = ‘010’AC Parameters for External Memory Interface Parameter Description Min Max Units134 Oscillator Diagram OscillatorsInternal H-F Oscillator Suspend Mode Programmable Internal High-Frequency H-F OscillatorSFR Definition 14.1. Oscicn Internal H-F Oscillator Control Ioscen Ifrdy Suspend IFCN1 IFCN0Calibrating the Internal L-F Oscillator Programmable Internal Low-Frequency L-F OscillatorOsccal SFR Definition 14.3. Osclcn Internal L-F Oscillator Control Osclen Osclrdy OSCLF3 OSCLF2 OSCLF1 OSCLF0 OSCLD1 OSCLD0External Oscillator Drive Circuit Clocking Timers Directly Through the External OscillatorExternal Crystal Example External RC Example External Capacitor ExampleXtlvld XOSCMD2 XOSCMD1 XOSCMD0 XFCN2 XFCN1 XFCN0 SFR Definition 14.4. Oscxcn External Oscillator ControlXfcn Clock Multiplier SFR Definition 14.5. Clkmul Clock Multiplier ControlMulen Mulinit Mulrdy Mulsel MulselExternal Oscillator Clock Signal Internal Oscillator Clock SignalSystem and USB Clock Selection System Clock SelectionSFR Definition 14.6. Clksel Clock Select Usbclk ClkslUsbclk ClkslOscillator Electrical Characteristics External USB Clock Requirements146 Port I/O Functional Block Diagram Port 0 through Port Port Input/OutputPort I/O Cell Block Diagram Crossbar Priority Decoder with No Pins Skipped Priority Crossbar DecoderCrossbar Priority Decoder with Crystal Pins Skipped Port I/O Initialization SFR Definition 15.1. XBR0 Port I/O Crossbar Register CP1AE CP1E CP0AE CP0E Syscke SMB0E SPI0E URT0ESFR Definition 15.2. XBR1 Port I/O Crossbar Register SFR Definition 15.3. XBR2 Port I/O Crossbar RegisterWeakpud Xbare T1E T0E Ecie PCA0ME URT1EGeneral Purpose Port I/O SFR Definition 15.5. P0MDIN Port0 Input ModeSFR Definition 15.4. P0 Port0 Latch SFR Definition 15.6. P0MDOUT Port0 Output Mode SFR Definition 15.7. P0SKIP Port0 SkipSFR Definition 15.10. P1MDOUT Port1 Output Mode SFR Definition 15.9. P1MDIN Port1 Input ModeSFR Definition 15.8. P1 Port1 Latch SFR Definition 15.11. P1SKIP Port1 Skip SFR Definition 15.13. P2MDIN Port2 Input ModeSFR Definition 15.12. P2 Port2 Latch SFR Definition 15.14. P2MDOUT Port2 Output Mode SFR Definition 15.15. P2SKIP Port2 SkipSFR Definition 15.18. P3MDOUT Port3 Output Mode SFR Definition 15.17. P3MDIN Port3 Input ModeSFR Definition 15.16. P3 Port3 Latch SFR Definition 15.19. P3SKIP Port3 Skip SFR Definition 15.20. P4 Port4 LatchSFR Definition 15.21. P4MDIN Port4 Input Mode SFR Definition 15.22. P4MDOUT Port4 Output ModePort I/O DC Electrical Characteristics USB0 Block Diagram Universal Serial Bus Controller USB0Endpoint Addressing Endpoint Addressing SchemeUSB Transceiver Endpoint Associated Pipes USB Protocol AddressPren Phyen Speed PHYTST1 PHYTST0 Dfrec SFR Definition 16.1. USB0XCN USB0 Transceiver ControlPHYTST10 USB Register Access USB0 Register Access SchemeSFR Definition 16.2. USB0ADR USB0 Indirect Address Busy Autord UsbaddrSFR Definition 16.3. USB0DAT USB0 Data USB Register Definition 16.4. Index USB0 Endpoint Index USB0 Controller RegistersIndex USB Clock Configuration USB Register Definition 16.5. Clkrec Clock Recovery ControlCommunication Speed USB Clock 4x Clock Multiplier Input CRE Crssen CrlowFifo Split Mode Fifo ManagementFifo Configurations Fifo AccessFifo Double Buffering FifodataFunction Addressing Function Configuration and ControlUSB Register Definition 16.7. Faddr USB0 Function Address 174 USB Register Definition 16.8. Power USB0 Power Isoud Usbinh Usbrst Resume Susmd SusenUSB Register Definition 16.9. Framel USB0 Frame Number Low InterruptsIN3 IN2 IN1 EP0 OUT3 OUT2 OUT1USB Register Definition 16.13. Cmint USB0 Common Interrupt SOF Rstint Rsuint SusintIN3E IN2E IN1E EP0E OUT3E OUT2E OUT1EEndpoint0 Serial Interface EngineSofe Rstinte Rsuinte Susinte Endpoint0 Setup Transactions Endpoint0 in TransactionsEndpoint0 OUT Transactions Ssuend Soprdy Sdstl Suend Dataend Ststl Inprdy Oprdy USB Register Definition 16.17. E0CSR USB0 Endpoint0 ControlSsuend Endpoints1-3 in Interrupt or Bulk Mode Configuring Endpoints1-3Controlling Endpoints1-3 Endpoints1-3 in Isochronous Mode Clrdt Ststl Sdstl Flush Undrun Fifone Inprdy A packet being transmittedControlling Endpoints1-3 OUT Endpoints1-3 OUT Interrupt or Bulk ModeDbien ISO Dirsel Fcdt Split Endpoints1-3 OUT Isochronous Mode Clrdt Ststl Sdstl Flush Daterr Ovrun Fifoful Oprdy Eocl Dboen ISOE0CH USB Transceiver Electrical Characteristics Receiver192 SMBus Block Diagram SMBusSMBus Configuration Supporting DocumentsSMBus Transaction ArbitrationUsing the SMBus SCL Low TimeoutSCL High SMBus Free Timeout Clock Low ExtensionTion Register on SMBus Configuration Register SMBus Clock Source SelectionEquation 17.1. Minimum SCL High and Low Times Equation 17.2. Typical SMBus Bit RateMinimum SDA Setup Time Minimum SDA Hold Time Minimum SDA Setup and Hold TimesExthold SFR Definition 17.1. SMB0CF SMBus Clock/Configuration Ensmb INH Busy Exthold Smbtoe Smbfte SMBCS1 SMBCS0SMB0CN Control Register SFR Definition 17.2. SMB0CN SMBus Control Master Txmode STA STO Ackrq Arblost ACKBit Set by Hardware When Cleared by Hardware When Sources for Hardware Changes to SMB0CNMaster Transmitter Mode SFR Definition 17.3. SMB0DAT SMBus DataSMBus Transfer Modes Data RegisterTypical Master Transmitter Sequence Master Receiver Mode Typical Master Receiver SequenceSlave Receiver Mode Typical Slave Receiver SequenceSlave Transmitter Mode Typical Slave Transmitter Sequence SMBus Status DecodingCurrent SMbus State Typical Response Options Values ReadStart Slave byte was transmitted No action required expect UART0 Block Diagram UART0Equation 18.1. UART0 Baud Rate Enhanced Baud Rate GenerationOperational Modes Uart Interconnect Diagram Bit UartBit Uart Timing Diagram Multiprocessor Communications Master Slave Device S0MODE MCE0 REN0 SFR Definition 18.1. SCON0 Serial Port 0 ControlTI0 RI0 SFR Definition 18.2. SBUF0 Serial UART0 Port Data Buffer Target Actual Baud Oscillator Timer Clock T1M Timer Baud Rate Error Divide Source Pre-scaleSCA1-SCA0 Rate bps Factor SelectUART1 Block Diagram UART1 C8051F340/1/4/5 OnlyBaud Rate Generator Settings for Standard Baud Rates Baud Rate GeneratorEquation 19.1. UART1 Baud Rate SBRLH1SBRLL1Data Format UART1 Timing Without Parity or Extra BitData Transmission Configuration and OperationData Reception Multiprocessor Communications OVR1 PERR1 THRE1 REN1 TBX1 RBX1 TI1 RI1 SFR Definition 19.1. SCON1 UART1 ControlFifo SFR Definition 19.2. SMOD1 UART1 Mode MCE1 S1PT1 S1PT0 PE1 S1DL1 S1DL0 XBE1 SBL1SB1RUN SFR Definition 19.3. SBUF1 UART1 Data BufferSB1PS1 SB1PS0 Rev 227 228 SPI Block Diagram Enhanced Serial Peripheral Interface SPI0Signal Descriptions Master Out, Slave In MosiMaster In, Slave Out Miso Serial Clock SCKSPI0 Master Mode Operation Multiple-Master Mode Connection Diagram SPI0 Slave Mode Operation SPI0 Interrupt SourcesMaster Mode Data/Clock Timing Serial Clock TimingSlave Mode Data/Clock Timing Ckpha = SPI Special Function Registers SFR Definition 20.1. SPI0CFG SPI0 ConfigurationSpibsy Msten Ckpha Ckpol Slvsel Nssin Srmt Rxbmt SFR Definition 20.2. SPI0CN SPI0 Control Spif Wcol Modf Rxovrn NSSMD1 NSSMD0 Txbmt SpienSFR Definition 20.4. SPI0DAT SPI0 Data SFR Definition 20.3. SPI0CKR SPI0 Clock RateSCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SPI Master Timing Ckpha = 10. SPI Slave Timing Ckpha = SPI Slave Timing Parameters Slave Mode Timing* See FigureOnly 242 Timers Timer 0 and TimerMode 0 13-bit Counter/Timer Timer 0 and Timer 1 Modes Timer 2 Modes Timer 3 ModesCounter/Timer Mode 1 16-bit Counter/TimerTR0 GATE0 INT0 T0 Mode 2 Block Diagram Mode 2 8-bit Counter/Timer with Auto-ReloadT0 Mode 3 Block Diagram Mode 3 Two 8-bit Counter/Timers Timer 0 OnlySFR Definition 21.1. Tcon Timer Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0SFR Definition 21.2. Tmod Timer Mode GATE1GATE0 T1M1 T1M0SFR Definition 21.3. Ckcon Clock Control T3MH T3ML T2MH T2ML T1M T0M SCA1 SCA0SCA1 SCA0 Prescaled ClockSFR Definition 21.4. TL0 Timer 0 Low Byte SFR Definition 21.5. TL1 Timer 1 Low ByteSFR Definition 21.6. TH0 Timer 0 High Byte SFR Definition 21.7. TH1 Timer 1 High ByteTimer Bit Timer with Auto-ReloadBit Timers with Auto-Reload T2MH T2XCLKTMR2H Clock Source T2ML T2XCLKTimer 2 Capture Mode T2SPLIT = ‘0’ Timer 2 Capture Mode T2SPLIT = ‘1’ SFR Definition 21.8. TMR2CN Timer 2 Control TF2H TF2L TF2LEN T2CE T2SPLIT TR2 T2CSS T2XCLKSFR Definition 21.11. TMR2L Timer 2 Low Byte SFR Definition 21.12. TMR2H Timer 2 High ByteTimer 3 16-Bit Mode Block Diagram T3MH T3XCLK TMR3H Clock SourceT3ML T3XCLK TMR3L Clock Source10. Timer 3 Capture Mode T3SPLIT = ‘0’ USB Start-of-Frame Capture11. Timer 3 Capture Mode T3SPLIT = ‘1’ SFR Definition 21.13. TMR3CN Timer 3 Control TF3H TF3L TF3LEN T3CE T3SPLIT TR3 T3CSS T3XCLKSFR Definition 21.16. TMR3L Timer 3 Low Byte SFR Definition 21.17. TMR3H Timer 3 High ByteProgrammable Counter Array PCA0 PCA Counter/Timer PCA Timebase Input OptionsCPS2 CPS1 CPS0 TimebasePCA0CPM Register Settings for PCA Capture/Compare Modules Operation ModeCapture/Compare Modules PWM16 Ecom Capp Capn MAT TOG EccfPCA Capture Mode Diagram Edge-triggered Capture ModePCA Software Timer Mode Diagram Software Timer Compare ModePCA High Speed Output Mode Diagram High Speed Output ModeFrequency Output Mode Equation 22.1. Square Wave Frequency OutputBit Pulse Width Modulator Mode Equation 22.2 -Bit PWM Duty CyclePCA 16-Bit PWM Mode Equation 22.3 -Bit PWM Duty CycleWatchdog Timer Mode Watchdog Timer OperationEquation 22.4. Watchdog Timer Offset in PCA Clocks Watchdog Timer Timeout Intervals1Watchdog Timer Usage PCA0CPL4SFR Definition 22.1. PCA0CN PCA Control Register Descriptions for PCACCF4 CCF3 CCF2 CCF1 CCF0 SFR Definition 22.2. PCA0MD PCA Mode Cidl Wdte Wdlck CPS2 CPS1 CPS0 ECFSFR Definition 22.3. PCA0CPMn PCA Capture/Compare Mode SFR Definition 22.5. PCA0H PCA Counter/Timer High Byte SFR Definition 22.4. PCA0L PCA Counter/Timer Low ByteSFR Definition 22.6. PCA0CPLn PCA Capture Module Low Byte SFR Definition 22.7. PCA0CPHn PCA Capture Module High Byte 23. C2 Interface 23.1. C2 Interface RegistersC2 Register Definition 23.1. C2ADD C2 Address C2 Register Definition 23.2. Deviceid C2 Device IDCode Command C2 Register Definition 23.3. Revid C2 Revision ID23.2. C2 Pin Sharing Typical C2 Pin SharingContact Information