Silicon Laboratories C8051F345, C8051F347 Crossbar Priority Decoder with Crystal Pins Skipped

C8051F340/1/2/3/4/5/6/7

			XTAL1	XTAL2	P0				CNVSTR	VREF
SF Signals
(32-pin
Package)
SF Signals									XTAL1	XTAL2
Package)
(48-pin
PIN I/O	0	1	2	3	4		5		6	7	0
TX0
RX0
SCK
MISO
MOSI
NSS*
SDA
SCL
CP0
CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
T0
T1
TX1**
RX1**
			1	1		0		0	0	0	0
	0	0
			P0SKIP[0:7]

			P1								P2								P3
																P3.1-P3.7 Unavailable on
																		32-pin Package
		ALE	CNVSTR	VREF	/RD	/WR
1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7

*NSS is only pinned out in 4-wire SPI mode

**UART1 Only in 48-pin Package

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
	P1SKIP[0:7]								P2SKIP[0:7]								P3SKIP[0:7]

Port pin potentially available to peripheral

SF Signals Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must be manually configured to skip their corresponding port pins.

Figure 15.4. Crossbar Priority Decoder with Crystal Pins Skipped

Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and SCL); when either UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions have been assigned.

Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a Port pin.

150 Rev. 0.5