C8051F340/1/2/3/4/5/6/7
SFR Definition 5.6. ADC0CN: ADC0 Control
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | Reset Value |
AD0EN
AD0TM
AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1
AD0CM0
00000000
Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | SFR Address: |
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| (bit addressable) | 0xE8 |
Bit7: | AD0EN: ADC0 Enable Bit. |
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| 0: ADC0 Disabled. ADC0 is in |
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| 1: ADC0 Enabled. ADC0 is active and ready for data conversions. |
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Bit6: | AD0TM: ADC0 Track Mode Bit. |
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| 0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion | |||||||
| is in progress. |
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| 1: |
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Bit5: | AD0INT: ADC0 Conversion Complete Interrupt Flag. |
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| 0: ADC0 has not completed a data conversion since the last time AD0INT was cleared. | |||||||
| 1: ADC0 has completed a data conversion. |
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Bit4: | AD0BUSY: ADC0 Busy Bit. |
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| Read: |
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| 0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set | |||||||
| to logic 1 on the falling edge of AD0BUSY. |
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| 1: ADC0 conversion is in progress. |
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| Write: |
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| 0: No Effect. |
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| 1: Initiates ADC0 Conversion if |
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Bit3: | AD0WINT: ADC0 Window Compare Interrupt Flag. |
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| 0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared. | |||||||
| 1: ADC0 Window Comparison Data match has occurred. |
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| When AD0TM = 0: |
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000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 1.
100: ADC0 conversion initiated on rising edge of external CNVSTR.
101: ADC0 conversion initiated on overflow of Timer 3.
11x: Reserved. When AD0TM = 1:
000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by conversion.
001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conversion.
010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion.
011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion.
100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge.
101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion.
11x: Reserved.
Rev. 0.5 | 51 |
