Silicon Laboratories C8051F342, C8051F347, C8051F346 SFR Definition 15.16. P3 Port3 Latch

C8051F340/1/2/3/4/5/6/7

SFR Definition 15.16. P3: Port3 Latch

R/W		R/W	R/W	R/W	R/W	R/W	R/W		R/W	Reset Value
P3.7		P3.6	P3.5	P3.4	P3.3	P3.2	P3.1		P3.0	11111111
Bit7		Bit6	Bit5	Bit4	Bit3	Bit2	Bit1		Bit0	SFR Address:
								(bit addressable)		0xB0
Bits7–0:	P3.[7:0]
	Write - Output appears on I/O pins.
	0: Logic Low Output.
	1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = 0).
	Read - Always reads ‘0’ if selected as analog input in register P3MDIN. Directly reads Port
	pin when configured as digital input.
	0: P3.n pin is logic low.
	1: P3.n pin is logic high.

Note: P3.1–3.7 are only available on 48-pin devices.

SFR Definition 15.17. P3MDIN: Port3 Input Mode

R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W		Reset Value
								11111111
Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0		SFR Address:

0xF4

Bits7–0: Analog Input Configuration Bits for P3.7–P3.0 (respectively).

Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled.

0: Corresponding P3.n pin is configured as an analog input.

1: Corresponding P3.n pin is not configured as an analog input.

Note: P3.1–3.7 are only available on 48-pin devices.

SFR Definition 15.18. P3MDOUT: Port3 Output Mode

R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W		Reset Value
								00000000
Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0		SFR Address:
									0xA7

Bits7–0: Output Configuration Bits for P3.7–P3.0 (respectively); ignored if corresponding bit in regis- ter P3MDIN is logic 0.

0: Corresponding P3.n Output is open-drain.

1: Corresponding P3.n Output is push-pull.

Note: P3.1–3.7 are only available on 48-pin devices.

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