Silicon Laboratories C8051F342, C8051F347 Equation 22.3 -Bit PWM Duty Cycle, PCA 16-Bit PWM Mode

C8051F340/1/2/3/4/5/6/7

22.2.6. 16-Bit Pulse Width Modulator Mode

A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare mod- ule defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the output on CEXn is asserted high; when the counter overflows, CEXn is asserted low. To output a varying duty cycle, new value writes should be synchronized with PCA CCFn match inter- rupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize the capture/compare register writes. The duty cycle for 16-Bit PWM Mode is given by Equation 22.3.

Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/ Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.

(65536 – PCA0CPn) DutyCycle = ----------------------------------------------------

65536

Equation 22.3. 16-Bit PWM Duty Cycle

Using Equation 22.3, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is 0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.

Write to

PCA0CPLn0

ENB

Reset

Write to

PCA0CPHn ENB

1

PCA0CPMn

P E C C M T P E W C A A A O W C M O P P T G M C 1 M P N n n n F

6 n n n n n

1 0 0 x 0 x

Enable

PCA Timebase

PCA0CPHn	PCA0CPLn
		match
16-bit Comparator			S SET	Q
			R CLR	Q
PCA0H	PCA0L
		Overflow

CEXn Crossbar Port I/O

Figure 22.9. PCA 16-Bit PWM Mode

Rev. 0.5 271