C8051F340/1/2/3/4/5/6/7

 

Table 9.3. Special Function Registers

(Continued)

SFRs are listed in alphabetical order. All undefined SFR locations are reserved.

Register

Address

Description

 

Page

SBUF0

0x99

UART0 Data Buffer

 

217

SCON0

0x98

UART0 Control

 

216

SMB0CF

0xC1

SMBus Configuration

 

200

SMB0CN

0xC0

SMBus Control

 

202

SMB0DAT

0xC2

SMBus Data

 

204

SMOD1

0xE5

UART1 Mode

 

225

SP

0x81

Stack Pointer

 

85

SPI0CFG

0xA1

SPI Configuration

 

236

SPI0CKR

0xA2

SPI Clock Rate Control

 

238

SPI0CN

0xF8

SPI Control

 

237

SPI0DAT

0xA3

SPI Data

 

238

TCON

0x88

Timer/Counter Control

 

247

TH0

0x8C

Timer/Counter 0 High

 

250

TH1

0x8D

Timer/Counter 1 High

 

250

TL0

0x8A

Timer/Counter 0 Low

 

250

TL1

0x8B

Timer/Counter 1 Low

 

250

TMOD

0x89

Timer/Counter Mode

 

248

TMR2CN

0xC8

Timer/Counter 2 Control

 

255

TMR2H

0xCD

Timer/Counter 2 High

 

256

TMR2L

0xCC

Timer/Counter 2 Low

 

256

TMR2RLH

0xCB

Timer/Counter 2 Reload High

 

256

TMR2RLL

0xCA

Timer/Counter 2 Reload Low

 

256

TMR3CN

0x91

Timer/Counter 3Control

 

261

TMR3H

0x95

Timer/Counter 3 High

 

262

TMR3L

0x94

Timer/Counter 3Low

 

262

TMR3RLH

0x93

Timer/Counter 3 Reload High

 

262

TMR3RLL

0x92

Timer/Counter 3 Reload Low

 

262

VDM0CN

0xFF

VDD Monitor Control

 

103

USB0ADR

0x96

USB0 Indirect Address Register

 

167

USB0DAT

0x97

USB0 Data Register

 

168

USB0XCN

0xD7

USB0 Transceiver Control

 

165

XBR0

0xE1

Port I/O Crossbar Control 0

 

152

XBR1

0xE2

Port I/O Crossbar Control 1

 

153

XBR2

0xE3

Port I/O Crossbar Control 2

 

153

All Other Addresses

Reserved

 

 

84

Rev. 0.5

Page 84
Image 84
Silicon Laboratories C8051F340, C8051F347, C8051F346, C8051F341, C8051F343, C8051F344, C8051F345, C8051F342 SBUF0, SPI0CN