Silicon Laboratories C8051F343, C8051F347, C8051F346 SMBus, UART0, UART1 C8051F340/1/4/5 Only

C8051F340/1/2/3/4/5/6/7
Figure 16.2. USB0 Register Access Scheme	166
Table 16.2. USB0 Controller Registers	169
Figure 16.3. USB FIFO Allocation	171
Table 16.3. FIFO Configurations	172
Table 16.4. USB Transceiver Electrical Characteristics	191
17.SMBus
Figure 17.1. SMBus Block Diagram	193
Figure 17.2. Typical SMBus Configuration	194
Figure 17.3. SMBus Transaction	195
Table 17.1. SMBus Clock Source Selection	198
Figure 17.4. Typical SMBus SCL Generation	199
Table 17.2. Minimum SDA Setup and Hold Times	199
Table 17.3. Sources for Hardware Changes to SMB0CN	203
Figure 17.5. Typical Master Transmitter Sequence	205
Figure 17.6. Typical Master Receiver Sequence	206
Figure 17.7. Typical Slave Receiver Sequence	207
Figure 17.8. Typical Slave Transmitter Sequence	208
Table 17.4. SMBus Status Decoding	209
18.UART0
Figure 18.1. UART0 Block Diagram	211
Figure 18.2. UART0 Baud Rate Logic	212
Figure 18.3. UART Interconnect Diagram	213
Figure 18.4. 8-Bit UART Timing Diagram	213
Figure 18.5. 9-Bit UART Timing Diagram	214
Figure 18.6. UART Multi-Processor Mode Interconnect Diagram	215
Table 18.1. Timer Settings for Standard Baud Rates
Using The Internal Oscillator	218
19. UART1 (C8051F340/1/4/5 Only)
Figure 19.1. UART1 Block Diagram	219
Table 19.1. Baud Rate Generator Settings for Standard Baud Rates	220
Figure 19.2. UART1 Timing Without Parity or Extra Bit	221
Figure 19.3. UART1 Timing With Parity	221
Figure 19.4. UART1 Timing With Extra Bit	221
Figure 19.5. Typical UART Interconnect Diagram	222
Figure 19.6. UART Multi-Processor Mode Interconnect Diagram	223
20.Enhanced Serial Peripheral Interface (SPI0)
Figure 20.1. SPI Block Diagram	229
Figure 20.2. Multiple-Master Mode Connection Diagram	232
Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram	232
Figure 20.4. 4-Wire Single Master Mode and Slave Mode Connection Diagram ...	232
Figure 20.5. Master Mode Data/Clock Timing	234
Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0)	235
Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1)	235
Figure 20.8. SPI Master Timing (CKPHA = 0)	239
Figure 20.9. SPI Master Timing (CKPHA = 1)	239

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