C8051F340/1/2/3/4/5/6/7
SFR Definition 21.4. TL0: Timer 0 Low Byte
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | Reset Value |
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| 00000000 |
Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | SFR Address: |
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| 0x8A |
Bits
The TL0 register is the low byte of the
SFR Definition 21.5. TL1: Timer 1 Low Byte
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | Reset Value |
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| 00000000 |
Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | SFR Address: |
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| 0x8B |
Bits
The TL1 register is the low byte of the
SFR Definition 21.6. TH0: Timer 0 High Byte
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | Reset Value |
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| 00000000 |
Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | SFR Address: |
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| 0x8C |
Bits
The TH0 register is the high byte of the
SFR Definition 21.7. TH1: Timer 1 High Byte
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | Reset Value |
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| 00000000 |
Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | SFR Address: |
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| 0x8D |
Bits
The TH1 register is the high byte of the
250 | Rev. 0.5 |