Silicon Laboratories C8051F340 Bit Timers with Auto-Reload, T2MH T2XCLK, TMR2H Clock Source

C8051F340/1/2/3/4/5/6/7

21.2.2. 8-bit Timers with Auto-Reload

When T2SPLIT = ‘1’ and T2CE = ‘0’, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers operate in auto-reload mode as shown in Figure 21.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is always running when configured for 8-bit Mode.

Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:

T2MH	T2XCLK	TMR2H Clock Source
0	0	SYSCLK / 12
0	1	External Clock / 8
1	X	SYSCLK

T2ML	T2XCLK	TMR2L Clock Source
0	0	SYSCLK / 12
0	1	External Clock / 8
1	X	SYSCLK

The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows from 0xFF to 0x00. When Timer 2 interrupts are enabled, an interrupt is generated each time TMR2H over- flows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is generated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags are not cleared by hardware and must be manually cleared by software.

	T2XCLK
SYSCLK / 12
	0
External Clock / 8	1

CKCON

T T T T T T S S 3 3 2 2 1 0 C C M M M M M M A A

H L H L 1 0

0

TR2

1

SYSCLK

1

0

TMR2RLH Reload

TCLK

TMR2H

TMR2RLL Reload

TCLK TMR2L

To SMBus

	TF2H	Interrupt
	TF2L
TMR2CN	TF2LEN
	T2CE
	T2SPLIT
	TR2
	T2CSS
	T2XCLK

To ADC,

SMBus

Figure 21.5. Timer 2 8-Bit Mode Block Diagram

252 Rev. 0.5