Silicon Laboratories C8051F346, C8051F347, C8051F341 CIP-51 Microcontroller, CIP-51 Block Diagram

C8051F340/1/2/3/4/5/6/7

9.CIP-51 Microcontroller

The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are four 16-bit counter/timers (see description in Section 21), an enhanced full-duplex UART (see description in Section 18), an Enhanced SPI (see description in Section 20), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (Section 9.2.6), and 25 Port I/O (see description in Sec- tion 15). The CIP-51 also includes on-chip debug hardware (see description in Section 23), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit.

The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram). The CIP-51 includes the following features:

-	Fully Compatible with MCS-51 Instruction				-	Extended Interrupt Handler
	Set				-	Reset Input
- 0 to 48 MHz Clock Frequency					- Power Management Modes
- 256 Bytes of Internal RAM					- On-chip Debug Logic
- 25 Port I/O					- Program and Data Memory Security
				DATA BUS
		D8				D8	D8
		D8		D8	B REGISTER		STACK POINTER
		ACCUMULATOR
	BUS	TMP1		TMP2
	DATA	PSW				SRAM	SRAM
			ALU			ADDRESS	(256 X 8)
						REGISTER
		D8	D8			D8	D8
				DATA BUS
		BUFFER					SFR_ADDRESS
				D8			SFR_CONTROL
						SFR
		DATA POINTER		D8	D8	BUS	SFR_WRITE_DATA
						INTERFACE
							SFR_READ_DATA
		PC INCREMENTER		BUS
		PROGRAM COUNTER (PC)			D8		MEM_ADDRESS
				DATA		MEMORY	MEM_CONTROL
		PRGM. ADDRESS REG.					MEM_WRITE_DATA
					A16	INTERFACE
							MEM_READ_DATA
		PIPELINE			D8
	RESET	CONTROL
	CLOCK	LOGIC					SYSTEM_IRQs
						INTERRUPT
	STOP				D8	INTERFACE	EMULATION_IRQ
		POWER CONTROL
	IDLE			D8
		REGISTER

Figure 9.1. CIP-51 Block Diagram

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