Silicon Laboratories C8051F342 USB Register Definition 16.17. E0CSR USB0 Endpoint0 Control

C8051F340/1/2/3/4/5/6/7

USB Register Definition 16.17. E0CSR: USB0 Endpoint0 Control

R/W	R/W	R/W	R	R/W	R/W	R/W	R
SSUEND	SOPRDY	SDSTL	SUEND	DATAEND	STSTL	INPRDY	OPRDY
Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0

Reset Value

00000000

USB Address:

	0x11
Bit7:	SSUEND: Serviced Setup End
	Write: Software should set this bit to ‘1’ after servicing a Setup End (bit SUEND) event.
	Hardware clears the SUEND bit when software writes ‘1’ to SSUEND.
	Read: This bit always reads ‘0’.
Bit6:	SOPRDY: Serviced OPRDY
	Write: Software should write ‘1’ to this bit after servicing a received Endpoint0 packet. The
	OPRDY bit will be cleared by a write of ‘1’ to SOPRDY.
	Read: This bit always reads ‘0’.
Bit5:	SDSTL: Send Stall
	Software can write ‘1’ to this bit to terminate the current transfer (due to an error condition,
	unexpected transfer request, etc.). Hardware will clear this bit to ‘0’ when the STALL hand-
	shake is transmitted.
Bit4:	SUEND: Setup End
	Hardware sets this read-only bit to ‘1’ when a control transaction ends before software has
	written ‘1’ to the DATAEND bit. Hardware clears this bit when software writes ‘1’ to
	SSUEND.
Bit3:	DATAEND: Data End
	Software should write ‘1’ to this bit:
	1. When writing ‘1’ to INPRDY for the last outgoing data packet.
	2. When writing ‘1’ to INPRDY for a zero-length data packet.
	3. When writing ‘1’ to SOPRDY after servicing the last incoming data packet.
	This bit is automatically cleared by hardware.
Bit2:	STSTL: Sent Stall
	Hardware sets this bit to ‘1’ after transmitting a STALL handshake signal. This flag must be
	cleared by software.
Bit1:	INPRDY: IN Packet Ready
	Software should write ‘1’ to this bit after loading a data packet into the Endpoint0 FIFO for
	transmit. Hardware clears this bit and generates an interrupt under either of the following
	conditions:
	1. The packet is transmitted.
	2. The packet is overwritten by an incoming SETUP packet.
	3. The packet is overwritten by an incoming OUT packet.
Bit0:	OPRDY: OUT Packet Ready
	Hardware sets this read-only bit and generates an interrupt when a data packet has been
	received. This bit is cleared only when software writes ‘1’ to the SOPRDY bit.

Rev. 0.5 183