C8051F340/1/2/3/4/5/6/7
15.1. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 15.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the Crossbar, its corresponding PnSKIP bit should be set. This applies to the VREF signal, external oscillator pins (XTAL1, XTAL2), the ADC’s external conversion start signal (CNVSTR), EMIF control signals, and any selected ADC or Comparator inputs. The PnSKIP registers may also be used to skip pins to be used as GPIO. The Crossbar skips selected pins as if they were already assigned, and moves to the next unas- signed pin. Figure 15.3 shows the Crossbar Decoder priority with no Port pins skipped. Figure 15.4 shows a Crossbar example with pins P0.2 and P0.3 skipped (P0SKIP = 0x0C).
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| P0 |
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| P1 |
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| P2 |
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| XTAL1 | XTAL2 |
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| CNVSTR | VREF |
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SF Signals |
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Package) |
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| XTAL1 | XTAL2 |
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| ALE |
| CNVSTR | VREF | /RD | /WR |
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SF Signals |
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PIN I/O | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 0 | 1 | 2 | 3 | 4 | 5 |
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TX0 |
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RX0 |
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SCK |
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MISO |
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MOSI |
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NSS* |
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| *NSS is only pinned out in |
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SDA |
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SCL |
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CP0 |
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CP0A |
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CP1 |
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CP1A |
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SYSCLK |
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CEX0 |
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CEX1 |
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CEX2 |
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CEX3 |
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CEX4 |
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ECI |
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T0 |
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T1 |
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TX1** |
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| **UART1 Only in |
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RX1** |
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| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | ||||
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| P0SKIP[0:7] |
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| P1SKIP[0:7] |
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| P2SKIP[0:7] |
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| P3SKIP[0:7] |
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Port pin potentially available to peripheral
SF Signals Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must be manually configured to skip their corresponding port pins.
Figure 15.3. Crossbar Priority Decoder with No Pins Skipped
Rev. 0.5 | 149 |