Silicon Laboratories C8051F343, C8051F347 SFR Definition 12.3. Flscl Flash Scale, Fose, Flrt

C8051F340/1/2/3/4/5/6/7

SFR Definition 12.3. FLSCL: Flash Scale

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

FOSE

Reserved Reserved

FLRT

Reserved Reserved Reserved Reserved

10000000

Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0	SFR Address:
								0xB6
Bits7:	FOSE: Flash One-shot Enable
	This bit enables the Flash read one-shot. When the Flash one-shot disabled, the Flash
	sense amps are enabled for a full clock cycle during Flash reads. At system clock frequen-
	cies below 10 MHz, disabling the Flash one-shot will increase system power consumption.

0:Flash one-shot disabled.

1:Flash one-shot enabled.

Bits6–5: RESERVED. Read = 00b. Must Write 00b.

Bit 4: FLRT: FLASH Read Time.

This bit should be programmed to the smallest allowed value, according to the system clock speed.

0:SYSCLK <= 25 MHz.

1:SYSCLK <= 48 MHz.

Bits3–0: RESERVED. Read = 0000b. Must Write 0000b.

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