C8051F340/1/2/3/4/5/6/7
18.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in
Timer 1
UART
TL1
Overflow
2 TX Clock
TH1
Start
Detected
RX Timer
Overflow
2 RX Clock
Figure 18.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2,
| T1CLK |
| 1 |
UartBaudRate = | ⋅ | ||
| (256 – T1H) |
| 2 |
Equation 18.1. UART0 Baud Rate
Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload value). Timer 1 clock frequency is selected as described in Section “21. Timers” on page 243. A quick reference for typical baud rates using the internal oscillator is given in Table 18.1. Note that the internal oscillator may still generate the system clock if an external oscillator is driving Timer 1.
18.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode
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