Silicon Laboratories C8051F346, C8051F347, C8051F341, C8051F343, C8051F340 SMBus Block Diagram

C8051F340/1/2/3/4/5/6/7

17. SMBus

The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data. Data can be transferred at up to 1/10th of the system clock as a master or slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A method of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus.

The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple mas- ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP control and generation. Three SFRs are associated with the SMBus: SMB0CF configures the SMBus; SMB0CN controls the status of the SMBus; and SMB0DAT is the data register, used for both transmitting and receiving SMBus data and slave addresses.

SMB0CN

M	T	S	S	A	A	A	S
A	X	T	T	C	R	C	I
S	M	A	O	K	B	K
T	O			R	L
E	D			Q	O
R	E				S
					T

SMB0CF

EI B E S S S S N N U X M M M M S H S T B B B B M Y H T F C C

B O O T S S

L E E 1 0 D

00 T0 Overflow

01 T1 Overflow

10 TMR2H Overflow

11 TMR2L Overflow

	SMBUS CONTROL LOGIC			FILTER	SCL
Interrupt	Arbitration
	SCL Synchronization		SCL	N	C
Request	SCL Generation (Master Mode)		Control
					R
	SDA Control
		Data Path	SDA		O
	IRQ Generation
		Control	Control		S	Port I/O
					S
					B
					A
					R
		SMB0DAT			SDA
		7 6 5 4 3 2 1 0		FILTER

N

Figure 17.1. SMBus Block Diagram

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