Silicon Laboratories C8051F347 PCA Counter/Timer, PCA Timebase Input Options, CPS2 CPS1 CPS0

C8051F340/1/2/3/4/5/6/7

22.1. PCA Counter/Timer

The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.

Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.

Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2-CPS0 bits in the PCA0MD register select the timebase for the counter/timer as shown in Table 22.1.

When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft- ware (Note: PCA0 interrupts must be globally enabled before CF interrupts are recognized. PCA0 inter- rupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit in EIE1 to logic 1). Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle mode.

Table 22.1. PCA Timebase Input Options

CPS2	CPS1	CPS0	Timebase
0	0	0	System clock divided by 12
0	0	1	System clock divided by 4
0	1	0	Timer 0 overflow
0	1	1	High-to-low transitions on ECI (max rate = system clock divided
			by 4)
1	0	0	System clock
1	0	1	External oscillator source divided by 8*

*Note: External oscillator source divided by 8 is synchronized with the system clock.

		IDLE
PCA0MD		PCA0CN
C W W C C C E		C C C C C C C
I D D P P P C		F R C C C C C
D T L	S S S F	F F F F F
L E C 2 1 0		4 3 2 1 0
K
SYSCLK/12	000
SYSCLK/4	001

Timer 0 Overflow

010

ECI

011

SYSCLK

100

External Clock/8

101

PCA0L

read

0

1

		To SFR Bus
Snapshot
Register
PCA0H	PCA0L	Overflow	To PCA Interrupt System
		CF
		To PCA Modules

Figure 22.2. PCA Counter/Timer Block Diagram

264 Rev. 0.5