Silicon Laboratories C8051F344, C8051F347 Data Format, UART1 Timing Without Parity or Extra Bit

C8051F340/1/2/3/4/5/6/7

19.2. Data Format

UART1 has a number of available options for data formatting. Data transfers begin with a start bit (logic low), followed by the data bits (sent LSB-first), a parity or extra bit (if selected), and end with one or two stop bits (logic high). The data length is variable between 5 and 8 bits. A parity bit can be appended to the data, and automatically generated and detected by hardware for even, odd, mark, or space parity. The stop bit length is selectable between short (1 bit time) and long (1.5 or 2 bit times), and a multi-processor com- munication mode is available for implementing networked UART buses. All of the data formatting options can be configured using the SMOD1 register, shown in SFR Definition 19.2. Figure 19.2 shows the timing for a UART1 transaction without parity or an extra bit enabled. Figure 19.3 shows the timing for a UART1 transaction with parity enabled (PE1 = 1). Figure 19.4 is an example of a UART1 transaction when the extra bit is enabled (XBE1 = 1). Note that the extra bit feature is not available when parity is enabled, and the second stop bit is only an option for data lengths of 6, 7, or 8 bits.

MARK	START
		D0	D1	DN-2	DN-1	STOP	STOP
	BIT
SPACE						BIT 1	BIT 2

BIT TIMES

Optional

N bits; N = 5, 6, 7, or 8

Figure 19.2. UART1 Timing Without Parity or Extra Bit

MARK	START
		D0	D1	DN-2	DN-1	PARITY	STOP	STOP
	BIT
SPACE							BIT 1	BIT 2

BIT TIMES

Optional

N bits; N = 5, 6, 7, or 8

Figure 19.3. UART1 Timing With Parity

MARK	START
		D0	D1	DN-2	DN-1	EXTRA	STOP	STOP
	BIT
SPACE							BIT 1	BIT 2

BIT TIMES

Optional

N bits; N = 5, 6, 7, or 8

Figure 19.4. UART1 Timing With Extra Bit

Rev. 0.5 221