Architecture 351
Tracking mode
In tracking mode, the DDP2 loop supplies an external clock reference to a
clock controller. Two DDP2 loops can operate in tracking mode,with one
defined as the primary reference source for clocksynchronization, the other
defined as the secondary reference source. The secondary reference acts
as a back-up to the primary reference.
As shown in Figure 96 "Clock Controller primary and secondary tracking"
(page 351), a system with dual CPUs can use two clock controllers (CC-0
and CC-1). One clock controller acts as a back-up to the other. The clock
controllers should be completely locked to the reference clock.
Free run (non-tracking) mode
The clock synchronization of the can operate in free-run mode if:
•no loop is defined as the primary or secondary clock reference,
•the primary and secondary references are disabled, or
•the primary and secondary references are in local (near end) alarm
Figure 96
Clock Controller primary and secondary tracking
Nortel Communication Server 1000
Circuit Card Reference
NN43001-311 01.04 Standard
Release 5.0 23 May 2008
Copyright© 2003-2008, Nor tel Networks
.