Nortel Networks 311 MISP network bus interface

Functional description 965
This interface uses shared Static Random Access Memory (SRAM) as a
communication exchange center between the CPU and the MPU. Both the
CPU and the MPU can access this memory over the transmit and receive
channels on the bus.
Information exchange between the CPU and the MISP is performed with
packetized messages transmitted over the CPU bus. This interface has a
16-bit data bus, an 18-bit address bus,and interrupt and read/wr ite control
lines.
This interface uses shared Static Random Access Memory (SRAM) as a
communication exchange center between the CPU and the MPU. Both the
CPU and the MPU can access this memory over the transmit and receive
channels on the bus.
MISP network bus interface
The network bus interface:
•converts bit interleaved serial data received from the network bus into
byte interleaved data for transmission overthe 32 time slots used by
the HDLC controller
•accepts byte interleaved data transmitted from the HDLC controller and
converts it into a bit interleaved data stream for transmission over the
network bus
The network bus interface:
•converts bit interleaved serial data received from the network bus into
byte interleaved data for transmission overthe 32 time slots used by
the HDLC controller
•accepts byte interleaved data transmitted from the HDLC controller and
converts it into a bit interleaved data stream for transmission over the
network bus
Power consumption
Powerconsumption is +5V at 2 A; +15V at 50 mA; and -15V at 50 mA.
Powerconsumption is +5V at 2 A; +15V at 50 mA; and -15V at 50 mA.
Nortel Communication Server 1000
Circuit Card Reference
NN43001-311 01.04 Standard
Release 5.0 23May 2008
Copyright© 2003-2008, Nor tel Networks
.