Nortel Networks 311 Digital phase lock loops, System clock specication and characteristics

912 NTAK20Clock Controller daughterboard
The phase difference is used for making frequency measurements, and
evaluating input jitter and PLL performance.
This circuit, under firmware control, enables a phase difference
measurement to be taken between the referenceentering the PLL and
the system clock. The phase difference is used for making frequency
measurements and evaluating input jitter and PLL performance.
Digital phase lock loops
The main digital PLL enables the clock controller to provide a system clock
to the CPU. This clock is both phase and frequency lockedto a known
incoming reference.
The hardware has a locking range of + 4.6 ppm for Stratum3 and + 50
ppm for Stratum 4 (CCITT).
A second PLL on the clock controller provides the means for monitoring
another reference. Note that the error signal of this PLL is routed to the
phase difference detector circuit so the microprocessor can process it.
The main digital PLL enables the clock controller. to provide a system clock
to the CPU. This clock is both phase and frequency lockedto a known
incoming reference.
The hardware has a locking range of + 4.6ppm for Stratum 3ND and + 50
ppm for Stratum 4 (CCITT).
A second PLL on board the clock controller provides the means for
monitoring another reference. Note that the error signal of this PLL is routed
to the phase differencedetector circuit so the microprocessor can process it.
The main digital PLL enables the clock controller to provide a system clock
to the CPU. This clock is both phase and frequency lockedto a known
incoming reference. The hardware has a locking range of + 4.6 ppm for
Stratum 3 and + 50 ppm for Stratum 4 (CCITT).
A second PLL on the clock controller provides the means for monitoring
another reference. Note that the error signal of this PLL is routed to the
phase difference detector circuit so the microprocessor can process it.
System clock specification and characteristics
Since the accuracy requirements for CCITT and EIA Stratum 3 are different,
it is necessary to have two TCVCXOs which feature different values of
frequency tuning sensitivity. See Table373 "System clock specification and
characteristics" (page 913).
Nortel Communication Server 1000
Circuit Card Reference
NN43001-311 01.04 Standard
Release 5.0 23 May 2008
Copyright© 2003-2008, Nor tel Networks
.