09.95
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SINUMERIK 840C (IA)
3.5.5 Timeout analysis
A write access to the communication or local bus is executed by the bus interface.
The processor immediately receives an acknowledgement and continues. (Buffe-
red access to communication/local bus). If a timeout occurs during such an ac-
cess, the current state of the registers of the processor and coprocessor give no
information as to the cause of the timeout.
The user can switch off buffered accesses to the communication and local bus
(e.g. to test STEP 5 programs during the installation phase) via machine data
(PLC operating system MD bits 6049.0). These accesses are then slower be-
cause the processor only receives an acknowledgement when the whole bus cy-
cle has finished.
Machine data 6049.0 must be set in order to be able to determine the exact cause
of a timeout.
3.6 Procedure for error search after PLC stop
The table below describes the procedure for an error search in the PLC after
alarm: PLC CPU failure has been displayed on the operator panel.
Step Description
1Alarm display on operator panel: PLC CPU failure
2LED on PLC CPU flashing: evaluate flashing frequency: for a descrip-
tion see error displays: “SINUMERIK 840C, Installation Lists”
3LED on PLC CPU permanently lit: USTACK, read out detailed error
coding, for operation see above in this section
4If the contents of the 1st error code word are 00FFH an error has oc-
curred in the FBs.
For an error description see Diagnostics Guide, Section Error mes-
sages
5If the contents of the 1st error code word are not equal to 00FFH, see
error description in Diagnostics Guide, Section Error messages
END OF SECTION
3 PLC Installation
3.5.5 Timeout analysis