Texas Instruments TMS320DM648 manual Raw Interlaced Display Vertical Timing Example

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Display Timing Examples

The vertical output timing for raw mode is shown in Figure 4-28. This example outputs the same 480-line window. Note that the raw display mode is typically noninterlaced for output to a monitor. This example shows the more complex interlaced case. The active field 1 is 242.5-lines high and active field 2 is

242.5-lines high. This example shows the 480-line image window centered in the screen. This results in an IMGVOFF1 of 2 lines and an IMGVOFF2 of 3 lines and also results in a non-data half-line at the end of field 1 and at the beginning of field 2 due to their non-integer line lengths.

The VBLNK and VSYNC signals are shown as they would be output for active-low operation. Note that only one of the two signals is actually available externally. The VBLNK and VSYNC edges for field 1 occur at the end of an active line so their XSTART/XSTOP values are set to 720 (start of blanking). For field 2, VBLNK and VSYNC edges occur during the middle of the active horizontal line so their XSTART/XSTOP values are set to 360.

The FLD output is setup to transition at the start of each analog field (start of vertical blanking). There is no EAV[F] bit in raw mode, so FLD1YSTRT is set to 1, FLD2YSTART is set to 263, FBITCLR and FBITSET are ignored. Note that FLD2XSTRT is 360 so that the field indicator output changes halfway through the line.

The active horizontal output column shows the output data during the active portion of the horizontal line. Note that in raw mode there is no blanking data value so the default value is output for the active portion of all non-image window lines.

Figure 4-28. Raw Interlaced Display Vertical Timing Example

FLCOUNT

525

1

2

3

4

Field￿1￿blanking

5

6

ILCOUNT

240

240

240

240

240

240

240

	A	A
FLD	VBLNK	VSYNC

Active

horizontal

output

Default￿value

Default￿value

Default￿value

Default￿value

Default￿value

Default￿value

Default￿value

19
20
21	Field￿1￿active
22
23
	Field￿1￿image
262
263
264
265
266

267Field￿2￿blanking

269

282

283

284

Field￿2￿active

285

286

Field￿2￿image

524

525

1

IMGVOFF1￿=￿2

IMGVSIZE1￿=￿240

IMGVOFF2￿=￿3

IMGVSIZE2￿=￿240

FRMHEIGHT =￿525

VBITSET1￿=￿n/a

VBITCLR1￿=￿n/a

VBITSET2￿=￿n/a

VBITCLR2￿=￿n/a

240

240

240

240

1

2

239

240

240

240

240

240

240

240

240

240

240

240

240

1

2

239

240

240

240

VBLNKXSTART1￿=￿720VSYNCXSTART1￿=￿720

VBLNKYSTART1￿=￿1VSYNCYSTART1￿=￿4

VBLNKXSTOP1￿-￿720VSYNCXSTOP1￿=￿720

VBLNKYSTOP1￿-￿21VSYNCYSTOP1￿=￿7

VBLNKXSTAR2￿=￿360VSYNCXSTART2￿=￿360

VBLNKYSTART2￿=￿263VSYNCYSTART2￿=￿266

VBLNKXSTOP2￿=￿360VSYNCXSTOP2￿=￿360

BLNKYSTOP2￿=￿283VSYNCYSTOP2￿=￿269

Default￿value

Default￿value

Default￿value

Default￿value

FIFO￿data

FIFO￿data

FIFO￿data

FIFO￿data

Default￿value

Default￿value

Default￿value

Default￿value

Default￿value

Default￿value

Default￿value

Default￿value

Default￿value

Default￿value

Default￿value

FIFO￿data

FIFO￿data

FIFO￿data

FIFO￿data

Default￿value

Default￿value

FLD1XSTART =￿720 FLD1YSTART =￿1 FLD2XSTART =￿360 FLD2YSTART =￿263

FBITSET =￿n/a

FBITCLR￿=￿n/a

AAssumes VCT1P bit in VPCTL is set to 1 (active-low output). VSYNC output when VCTL2S bit in VDCTL is set to 00, VBLNK output when VCTL2S bit is set 01.

SPRUEM1 –May 2007	Video Display Port	115
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