Texas Instruments TMS320DM648 manual Bit Locked Raw Video Display Fifo Configuration

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Video Port FIFO

For locked raw video, the FIFO is split into channel A and B. The channels are locked together and use the same clock and control signals. Each channel uses a single buffer and write register (YDSTx) as shown in Figure 1-8.

For 16-bit raw video, the FIFO is configured as a single buffer, as shown in Figure 1-9. The FIFO outputs data on VDOUT[19-2]. The FIFO has a single read pointer and write register (YDSTA).

Figure 1-8. 8-Bit Locked Raw Video Display FIFO Configuration

YDSTA

Display FIFO A

64

VDOUT[9−2]

8

Buffer A (2560 bytes)

YDSTB

Display FIFO B

64

VDOUT[19−12]

8

Buffer B (2560 bytes)

Figure 1-9. 16-Bit Raw Video Display FIFO Configuration

YDSTA

64

Display FIFO

VDOUT[19−2]

16

Data Buffer (5120 bytes)

24 Overview SPRUEM1 –May 2007

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