Texas Instruments TMS320DM648 manual

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						Video Display Registers
	Table 4-7. Video Display Control Register (VDCTL) Field Descriptions					(continued)
				Description
Bit	field (1)	symval (1)	Value	BT.656 and Y/C Mode	Raw Data Mode
23	FXS	OF(value)		Field external synchronization enable bit.
		DEFAULT	0	VCTL3 is an output.
		OUTPUT
		FSINPUT	1	VCTL3 is an external field sync input.
22	VXS	OF(value)		Vertical external synchronization enable bit.
		DEFAULT	0	VCTL2 is an output.
		OUTPUT
		VSINPUT	1	VCTL2 is an external vertical sync input.
21	HXS	OF(value)		Horizontal external synchronization enable bit.
		DEFAULT	0	VCTL1 is an output.
		OUTPUT
		HSINPUT	1	VCTL1 is an external horizontal sync input.
20	VCTL3S	OF(value)		VCTL3 output select bit.
		DEFAULT	0	Output CBLNK
		CBLNK
		FLD	1	Output FLD
19-18	VCTL2S	OF(value)	0-3h	VCTL2 output select bit.
		DEFAULT	0	Output VSYNC
		VYSYNC
		VBLNK	1h	Output VBLNK
		CSYNC	2h	Output CSYNC
		FLD	3h	Output FLD
17-16	VCTL1S	OF(value)	0-3h	VCTL1 output select bit.
		DEFAULT	0	Output HSYNC
		HYSYNC
		HBLNK	1h	Output HBLNK
		AVID	2h	Output AVID
		FLD	3h	Output FLD
15	VDEN	OF(value)		Video display enable bit. Other bits in VDCTL (except RSTCH and BLKDIS bits) may
				only be changed when VDEN = 0.
		DEFAULT	0	Video display is disabled.
		DISABLE
		ENABLE	1	Video display is enabled.
14	Reserved	-	0	Reserved. The reserved bit location is always read as 0. A value written to this field
				has no effect.
13	RGBX	OF(value)		RGB extract enable bit.
		DEFAULT	0	Not used.
		DISABLE
		ENABLE	1	Not used.	Perform	FIFO unpacking.
12	RSYNC	OF(value)		Second, synchronized raw data channel enable bit.
		DEFAULT	0	Not used.	Second, synchronized raw data channel
					is disabled.
		DISABLE
		ENABLE	1	Not used.	Second, synchronized raw data channel
					is enabled.

SPRUEM1 –May 2007	Video Display Port	125
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Texas Instruments TMS320DM648 manual Video Display Control Register Vdctl Field Descriptions

Contents

Users Guide Submit Documentation Feedback Contents Raw Data Capture Mode BT.656 Image Display Video Display Registers Recommended Values Operational Details List of Figures Bit BT.656 Fifo Unpacking Video Display Event Register Vddispevt List of Tables Video Display Register Recommended Values Related Documentation From Texas Instruments About This ManualNotational Conventions Related Documentation From Texas Instruments Trademarks Overview Video Port Video Port Block Diagram Edma Interface Video Port Fifo BT.656 Video Capture Fifo Configuration Video Capture Fifo Configurations Ysrca Y/C Video Capture Fifo Configuration Bit Raw Video Capture Fifo Configuration Video Display Fifo Configurations Bit Locked Raw Video Display Fifo Configuration Video Port Registers 10. Y/C Video Display Fifo Configuration Video Port Pin Mapping Video Capture Signal Mapping1Video Display Signal Mapping Vdin Data Bus Usage for Capture Modes1 Capture Mode BT.656 Raw Data Data Bus BitVdin Bus Usage for Capture Modes Video Port Pin Multiplexing Vdout Data Bus Usage for Display ModesVideoPort Clocking Vdout Data Bus Usage for Display Modes1 Video Port Power-On Reset Reset OperationPeripheral Bus Reset Software Port Reset Interrupt Operation Capture Channel ResetDisplay Channel Reset Capture Edma Event Generation Edma Operation Edma Size and Threshold Restrictions Display Edma Event Generation Video Port Control Registers Edma Interface OperationVideo Port Control Registers Acronym Register Name Description Video Port Control Register VpctlVideo Port Control Register Vpctl Field Descriptions Operating Mode Video Port Operating Mode Selection Video Port Status Register Vpstat Field Descriptions Video Port Status Register Vpstat Video Port Interrupt Enable Register Vpie Lfda Dcna Lfda Sfda VINTA2 VINTA1 Serra Ccmpa Covra Video Port Interrupt Status Register Vpis Video Port Interrupt Status Register Vpis Field Descriptions Vdctl None Clear Short field detected on channel a interrupt detected bit Covra Video Capture Port BT.656 and Y/C Mode Field and Frame Operation BT.656 Video Capture Mode Video Capture Mode SelectionVideo Capture Mode Selection 1 BT.656 Capture Channels BT.656 Protection Bits Error Correction by Protection Bits Video Capture Parameters 3 BT.656 Image Window and Capture 5 BT.656 Fifo Packing 4 BT.656 Data SamplingCommon Video Source Parameters Video Source 1 Y/C Capture Channels Y/C Video Capture Mode2 Y/C Timing Reference Codes 3 Y/C Image Window and Capture 4 Y/C Fifo Packing BT.656 and Y/C Mode Field and Frame OperationBit Y/C Fifo Packing Vclkina Capture Determination and Notification BT.656 and Y/C Mode Capture OperationVC xCTL Bit Operation Vertical Synchronization Vertical Counter Reset PointVertical Synchronization Programming EAV VRST=0 VRST=1 FINV=0 FINV=1 Vcount Vcount Operation Example EXC = Horizontal Synchronization Horizontal Counter Reset PointHorizontal Synchronization Programming VCxCTL Bit Field Detect Method Field IdentificationField Identification Programming Video Input Filtering Short and Long Field DetectVclkin VSYNC# VCTL2 HSYNC# VCTL1 Input Filter Modes 10. Input Filter Mode SelectionChrominance Re-sampling Operation Scaling Operation 2 Scaled Co-Sited Filtering Edge Pixel Replication 11. Edge Pixel Replication Ancillary Data Capture Horizontal Ancillary Hanc Data Capture Raw Data Capture ModeVertical Ancillary Vanc Data Capture Raw Data Capture Notification Frmc 11. Raw Data Mode Capture OperationRaw Data Fifo Packing TCI Data Capture TCI Capture ModeTCI Capture Features PCR TCI Capture Error DetectionSynchronizing the System Clock TCI Data Capture Notification 12. TCI Capture Mode OperationVcactl Bit Clear Frmc Perr Psterr Writing to the FifoReading from the Fifo Capture Line Boundary Conditions Capturing Video in BT.656 or Y/C Mode Capturing Video in Raw Data Mode Handling Fifo Overrun in BT.656 or Y/C Mode Capturing Data in TCI Capture Mode Handling Fifo Overrun Condition in Raw Data Mode 13. Video Capture Control Registers Handling Fifo Overrun Condition in TCI Capture ModeVideo Capture Registers Vcfld Vcxpos Video Capture Channel x Status Register VCASTAT, VcbstatFsync Frmc F2C F1C Vcypos Description Bit BT.656 or Y/C Mode Raw Data Mode TCI ModeVideo Capture Channel a Control Register Vcactl Rstch Blkcap None ResetRdfe Finv EXC Fldd Vrst Hrst Vcen Lfde Sfde Resmpl Eavfid FDL Eavsav ExternV1EAV V0EAV Video Capture Channel x Field 1 Start Register VCxSTRT1 Value BT.656 or Y/C Mode Raw Data Mode TCI Mode Video Capture Channel x Field 1 Stop Register VCxSTOP1 Vcxstop Video Capture Channel x Field 2 Start Register VCxSTRT2Vcystop 26. Video Capture Channel x Field 2 Stop Register VCxSTOP2 Video Capture Channel x Field 2 Stop Register VCxSTOP2 Video Capture Channel x Vertical Interrupt Register VCxVINT VCTHRLD1 VCTHRLD2 Video Capture Channel B Control Register Vcbctl Video Capture Channel x Event Count Register VCxEVTCTCAPEVTCT2 CAPEVTCT1 Vrst Hrst Vcen 30. Video Capture Channel B Control Register Vcbctl SAV or VCTL1 inactive edge Not used 24. TCI Capture Control Register Tcictl Field Descriptions BT.656, Y/C Mode, or Raw Data Mode TCI ModeTCI Capture Control Register Tcictl Inpcr TCI Clock Initialization LSB Register Tciclkinitl TCI System Time Clock LSB Register Tcistclkl Bit Value ModeTCI Clock Initialization MSB Register Tciclkinitm TCI System Time Clock MSB Register Tcistclkm Default PcrmPcre Pcrm Pcre ATC TCI System Time Clock Compare LSB Register TcistcmplTCI System Time Clock Compare MSB Register Tcistcmpm TCI System Time Clock Compare Mask LSB Register Tcistmskl Value BT.656, Y/C Mode, or Raw Data Mode TCI ModeTCI System Time Clock Compare Mask MSB Register Tcistmskm Atcm Tickct Value BT.656, Y/C Mode, or Raw Data Mode TCI M odeTCI System Time Clock Ticks Interrupt Register Tciticks Video Capture Fifo Registers Capture Mode Register BT.656 or Y/C Raw Data34. Video Capture Fifo Registers 35. Video Capture Fifo Registers Function Video Display Registers Recommended Values Displaying Video in BT.656 or Y/C ModeVideo Display Field and Frame Operation Video Display Mode Selection Video Display Mode SelectionDmode Bits Mode Description Image Timing Smpte 296M Compatible Progressive Scan Display Interlaced Blanking Intervals and Video Areas Progressive Blanking Intervals and Video Area Video Display Counters Horizontal Blanking and Horizontal Sync Timing BT.656 Video Display Mode Sync Signal GenerationExternal Sync Operation Port Sync Operation Fpcount Vclkout Display Timing Reference Codes Line Number BT.656 Frame TimingLine Number 525/60 Description 3 BT.656 Image Display Blanking Codes4 BT.656 Fifo Unpacking Vclkout 1 Y/C Display Timing Reference Codes Y/C Video Display Mode2 Y/C Blanking Codes 3 Y/C Image Display 4 Y/C Fifo Unpacking Output Filter Mode SelectionVideo Output Filtering Output Filter Modes 2x Co-Sited Scaling 15. Chrominance Re-sampling 18. Output Edge Pixel Replication 2x Interspersed Scaling Ancillary Data Display Raw Data Display ModeHorizontal Ancillary Hanc Data Display Vertical Ancillary Vanc Data Display Raw Data Fifo Unpacking Raw Mode RGB Output Support Display Determination and Notification Video Display Field and Frame OperationDisplay Operation Vdctl Bit Display Line Boundary Conditions Video Display Event Generation Interlaced BT.656 Timing Example Display Timing ExamplesIpcount =IMGSIZE78 Yfifo Frmwidth = IMGHOFF1 = Vclkin Fpcount Ipcount VCTL1 Hblnkac VCTL1 Hsyncac VclkoutFlcount 112 26. BT.656 Interlaced Display Vertical Timing Example Interlaced Raw Display Example VCTL1 Hsyncab Vclkout Vclkin FpcountIpcount VCTL1 Hblnkab 28. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example Hsyncstart = 1350 Hsyncstop = VCTL1 Hblnkac VCTL1 Hsyncac VclkoutFrmwidth = IMGHOFF1 = Hblnkstart = Flcount EAV Ilcount V F 30. Y/C Progressive Display Vertical Timing Example Displaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Handling Under-run Condition of the Display Fifo Video Display Control Registers Video Display RegistersVideo Display Status Register Vdstat Video Display Status Register Vdstat Field Descriptions Video Display Control Register Vdctl Video Display Control Register Vdctl Field Descriptions BT.656 and Y/C Mode Raw Data Mode Video Display Control Register Vdctl Field Descriptions Blanking Value BT.656 and Y/C Mode Raw Data ModeNone Frmdis None Flddis Video Display Horizontal Blanking Register Vdhblnk Video Display Frame Size Register VdfrmszFrmheight Frmwidth Field has no effect BT.656 and Y/C Mode Raw Data Mode 31-28 Reserved VBLNKXSTOP1 VBLNKYSTOP1 VBLNKXSTART2 VBLNKYSTART2 DEFAULT0 Value BT.656 and Y/C ModeVBLNKYSTOP2 VBLNKXSTOP2 IMGVOFF1 Video Display Field 1 Image Offset Register VDIMGOFF1IMGHOFF1 None Negoff IMGHSIZE1 Video Display Field 1 Image Size Register VDIMGSZ1IMGVSIZE1 IMGHOFF2 Video Display Field 2 Image Offset Register VDIMGOFF2IMGVOFF2 Video Display Field 1 Timing Register VDFLDT1 Video Display Field 2 Image Size Register VDIMGSZ2IMGVSIZE2 IMGHSIZE2 FLD1YSTART Video Display Field 2 Timing Register VDFLDT2FLD1XSTART FLD2YSTART VDTHRLD2 Video Display Threshold Register VdthrldIncpix VDTHRLD1 Hsyncstart Video Display Horizontal Synchronization Register VdhsyncHsyncstop VSYNCYSTART1 VSYNCXSTART1VSYNCYSTOP1 VSYNCXSTOP1 VSYNCYSTART2 VSYNCXSTART2 Vrld Video Display Counter Reload Register VdreloadCrld Hrld Crld Video Display Clipping Register Vdclip Video Display Event Register VddispevtDISPEVT2 DISPEVT1 Clipchigh Video Display Default Display Value Register Vddefval Crdefval Cbdefval Video Display Vertical Interrupt Register VdvintDefval Crdefval 56. Video Display Vertical Interrupt Register Vdvint Video Display Field Bit Register Vdfbit Fbitclr FbitsetVBITCLR1 VBITSET1 VBITSET2 VBITCLR2 Register Field 525/60 Value Video Display Registers Recommended Values34. Video Display Register Recommended Values Video Display Fifo Registers Display Mode35. Video Display Fifo Registers 36. Video Display Fifo Registers Function General-Purpose I/O Operation Offset Address Acronym Register Name Gpio RegistersVideo Port Registers Type Video Port Peripheral Identification Register VppidClass Revision Class Peren Soft Free Video Port Peripheral Control Register PCRPeren Stop Video Port Pin Function Register Pfunc Field Descriptions Video Port Pin Function Register Pfunc Normal VDATA0TO9 Normal VDATA10TO19 Video Port Pin Direction Register Pdir Field Descriptions Video Port Pin Direction Register Pdir VDATA8TO9IN VDATA8TO9OUT VDATA12TO15IN VDATA12TO15OUTVDATA4TO7IN VDATA4TO7OUT VDATA0T32IN VDATA0T32OUT Video Port Pin Data Input Register Pdin Field Descriptions Video Port Pin Data Input Register Pdin Video Port Pin Data Out Register Pdout Field Descriptions Video Port Pin Data Output Register PdoutPDOUT9 PDOUT8 PDOUT7 PDOUT6 PDOUT5 PDOUT4 PDOUT3 PDOUT2 PDOUT22 When writing data, writes to PDOUT20 bit Video Port Pin Data Set Register Pdset Field Descriptions Video Port Pin Data Set Register Pdset Video Port Pin Data Clear Register Pdclr Field Descriptions Video Port Pin Data Clear Register Pdclr PIEN22 Video Port Pin Interrupt Enable Register PienPIEN9 PIEN8 PIEN7 PIEN6 PIEN5 PIEN4 PIEN3 PIEN2 Value Description Video Port Pin Interrupt Polarity Register Pipol PISTAT22 Video Port Pin Interrupt Status Register PistatNone VCTL3INT None VCTL2INT PICLR22 Video Port Pin Interrupt Clear Register PiclrPICLR9 PICLR8 PICLR7 PICLR6 PICLR5 PICLR4 PICLR3 PICLR2 Vcxo Interpolated Control Port VIC Port Signal Direction Description VIC Port Interface SignalsOverview Interface Example Values for Interpolation Rate Operational Details VIC Port Registers Enabling VIC PortVIC Port Registers VIC Control Register Vicctl Field Descriptions VIC Control Register Vicctl Vicinbits VIC Input Register VicinVIC Input Register Vicin Field Descriptions Vicclkdiv VIC Clock Divider Register VicdivVIC Clock Divider Register Vicdiv Field Descriptions Rfid Products ApplicationsDSP