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EDMA Operation
∙Display complete not acknowledged (DCNA) bit is set.
∙GPIO interrupt (GPIO) bit is set.
The interrupt signal is a pulse only and does not hold state. The interrupt pulse is generated only when the number of set flags in VPIS transitions from none to one or more. Another interrupt pulse is not generated by setting additional flag bits.
Interrupts can be masked via the video port interrupt enable register (VPIE) using individual interrupt enables and the VIE global enable bit. The interrupts are cleared in the video port interrupt status register (VPIS) using the individual status bits. Writing a 1 to the appropriate bit clears the interrupt. The clearing of an interrupt flag reenables the generation of another interrupt pulse, if other flags are still set. In other words, pulse generation is reenabled by writing a 1 to any set bit of VPIS.
Upon receiving an interrupt you should:
1.Read VPIS.
2.Perform the service routine for whatever bits are set.
3.Clear appropriate bits by writing a 1 to their VPIS locations.
4.Upon return from the ISR, if VPIS bits have been (or remain) set, then another interrupt will occur.
2.3EDMA Operation
The video port uses up to three EDMA events per channel for a total of six possible events. Each EDMA event uses a dedicated event output. The outputs are:
∙ VPYEVTA ∙ VPCbEVTA ∙ VPCrEVTA
∙ VPYEVTB ∙ VPCbEVTB ∙ VPCrEVTB
2.3.1 Capture EDMA Event Generation
Capture EDMA events are generated based on the state of the capture FIFO(s). If no EDMA event is currently pending and the FIFO crosses the value specified by VCTHRLDn, an EDMA event is generated. Once an event has been requested, another EDMA event may not be generated until the servicing of the outstanding event has begun (as indicated by the first read of the FIFO by the EDMA event service). If the capture FIFO level exceeds 2x the VCTHRLDn value before the requested EDMA event completes, then another EDMA event may be generated. Thus, up to one EDMA event may be outstanding.
An outgoing data counter counts data read by the EDMA. This counter is loaded with the VCTHRLDn value whenever a new EDMA service begins. The counter then counts down for each
For BT.656 and Y/C modes, there are three FIFOs, one for each of the Y, Cb, and Cr color components. Each FIFO generates its own EDMA event; therefore, the EDMA event state and FIFO thresholds for each FIFO are tracked independently. The Cb and Cr FIFOs use a threshold value of 1/2 (VCTHRLDn + VCTHRLDnmod 2).
Because the capture FIFOs may hold multiple thresholds worth of data, a problem arises at the boundaries between fields. Since Field 1 and Field 2 may have different threshold values, the amount of data in the FIFO required to generate the EDMA event changes depending on the current capture field and the field of any outstanding EDMA requests. Similarly, the threshold value loaded in the outgoing data counter needs to change depending on which field'sEDMA event is being serviced (not which field is currently being captured). To prevent confusion at the field boundaries, the VCxEVTCT register is programmed to indicate the number of events to generate for each field. An event counter tracks how many events have been generated and indicates which threshold value to use in event generation and in the outgoing data counter. After the last Field 1 event has been generated, the EDMA logic looks for FIFO
>THRSHLD1 + THRSHLD2 to
32 | Video Port | SPRUEM1 |
