Texas Instruments TMS320DM648 specs

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				Video Port Control Registers
	Table 2-6. Video Port Interrupt Status Register (VPIS) Field Descriptions (continued)
Bit	field (1)	symval (1)	Value	Description
7	LFDA	OF(value)		Long field detected on channel A interrupt detected bit. (A long field is only detected
				when the VRST bit in VCACTL is cleared to 0; when VRST = 1, a long field is always
				detected.)
				BT.656 or Y/C capture mode - LFDA is set when long field detection is enabled and
				VCOUNT is not reset before VCOUNT = YSTOP + 1.
				Raw data mode, or TCI capture mode or display mode - Not used.
		DEFAULT	0	No interrupt is detected.
		NONE
		CLEAR	1	Interrupt is detected. Bit is cleared.
6	SFDA	OF(value)		Short field detected on channel A interrupt detected bit.
				BT.656 or Y/C capture mode - SFDA is set when short field detection is enabled and
				VCOUNT is reset before VCOUNT = YSTOP.
				Raw data mode, or TCI capture mode or display mode - Not used.
		DEFAULT	0	No interrupt is detected.
		NONE
		CLEAR	1	Interrupt is detected. Bit is cleared.
5	VINTA2	OF(value)		Channel A field 2 vertical interrupt detected bit.
				BT.656, or Y/C capture mode or any display mode - VINTA2 is set when a vertical
				interrupt occurred in field 2.
				Raw data mode or TCI capture mode - Not used.
		DEFAULT	0	No interrupt is detected.
		NONE
		CLEAR	1	Interrupt is detected. Bit is cleared.
4	VINTA1	OF(value)		Channel A field 1 vertical interrupt detected bit.
				BT.656, or Y/C capture mode or any display mode - VINTA1 is set when a vertical
				interrupt occurred in field 1.
				Raw data mode or TCI capture mode - Not used.
		DEFAULT	0	No interrupt is detected.
		NONE
		CLEAR	1	Interrupt is detected. Bit is cleared.
3	SERRA	OF(value)		Channel A synchronization error interrupt detected bit.
				BT.656 or Y/C capture mode - Synchronization parity error on channel A. An SERRA
				typically requires resetting the channel (RSTCH) or the port (VPRST).
				Raw data mode or TCI capture mode - Not used.
		DEFAULT	0	No interrupt is detected.
		NONE
		CLEAR	1	Interrupt is detected. Bit is cleared.
2	CCMPA	OF(value)		Capture complete on channel A interrupt detected bit. (Data is not in memory until the
				EDMA transfer is complete.)
				BT.656 or Y/C capture mode - CCMPA is set after capturing an entire field or frame
				(when F1C, F2C, or FRMC in VCASTAT are set) depending on the CON, FRAME,
				CF1, and CF2 control bits in VCACTL.
				Raw data mode - If RDFE bit is set, CCMPA is set when F1C, F2C, or FRMC in
				VCASTAT is set (when the data counter = the combined VCYSTOP/VCXSTOP value)
				depending on the CON, FRAME, CF1, and CF2 control bits in VCACTL. If RDFE bit is
				not set, CCMPA is set when FRMC in VCASTAT is set (when the data counter = the
				combined VCYSTOP/VCXSTOP value)
				TCI capture mode - CCMPA is set when FRMC in VCASTAT is set (when the data
				counter = the combined VCYSTOP/VCXSTOP value).
		DEFAULT	0	No interrupt is detected.
		NONE
		CLEAR	1	Interrupt is detected. Bit is cleared.
SPRUEM1 –May 2007				Video Port	43
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Texas Instruments TMS320DM648 manual Short field detected on channel a interrupt detected bit

Contents

Users Guide Submit Documentation Feedback Contents Raw Data Capture Mode BT.656 Image Display Video Display Registers Recommended Values Operational Details List of Figures Bit BT.656 Fifo Unpacking Video Display Event Register Vddispevt List of Tables Video Display Register Recommended Values Notational Conventions About This ManualRelated Documentation From Texas Instruments Related Documentation From Texas Instruments Trademarks Overview Video Port Video Port Block Diagram Edma Interface Video Port Fifo BT.656 Video Capture Fifo Configuration Video Capture Fifo Configurations Ysrca Y/C Video Capture Fifo Configuration Bit Raw Video Capture Fifo Configuration Video Display Fifo Configurations Bit Locked Raw Video Display Fifo Configuration Video Port Registers 10. Y/C Video Display Fifo Configuration Video Display Signal Mapping Video Capture Signal Mapping1Video Port Pin Mapping Vdin Bus Usage for Capture Modes Capture Mode BT.656 Raw Data Data Bus BitVdin Data Bus Usage for Capture Modes1 Vdout Data Bus Usage for Display Modes1 Vdout Data Bus Usage for Display ModesVideo Port Pin Multiplexing VideoPort Clocking Video Port Software Port Reset Reset OperationPower-On Reset Peripheral Bus Reset Display Channel Reset Capture Channel ResetInterrupt Operation Capture Edma Event Generation Edma Operation Edma Size and Threshold Restrictions Display Edma Event Generation Acronym Register Name Edma Interface OperationVideo Port Control Registers Video Port Control Registers Video Port Control Register Vpctl Field Descriptions Video Port Control Register VpctlDescription Operating Mode Video Port Operating Mode Selection Video Port Status Register Vpstat Field Descriptions Video Port Status Register Vpstat Video Port Interrupt Enable Register Vpie Lfda Dcna Lfda Sfda VINTA2 VINTA1 Serra Ccmpa Covra Video Port Interrupt Status Register Vpis Video Port Interrupt Status Register Vpis Field Descriptions Vdctl None Clear Short field detected on channel a interrupt detected bit Covra Video Capture Port BT.656 and Y/C Mode Field and Frame Operation 1 BT.656 Capture Channels Video Capture Mode SelectionBT.656 Video Capture Mode Video Capture Mode Selection BT.656 Protection Bits Error Correction by Protection Bits Video Capture Parameters 3 BT.656 Image Window and Capture Video Source 4 BT.656 Data Sampling5 BT.656 Fifo Packing Common Video Source Parameters 3 Y/C Image Window and Capture Y/C Video Capture Mode1 Y/C Capture Channels 2 Y/C Timing Reference Codes Vclkina BT.656 and Y/C Mode Field and Frame Operation4 Y/C Fifo Packing Bit Y/C Fifo Packing Operation BT.656 and Y/C Mode Capture OperationCapture Determination and Notification VC xCTL Bit EAV Vertical Counter Reset PointVertical Synchronization Vertical Synchronization Programming VRST=0 VRST=1 FINV=0 FINV=1 Vcount Vcount Operation Example EXC = VCxCTL Bit Horizontal Counter Reset PointHorizontal Synchronization Horizontal Synchronization Programming Field Identification Programming Field IdentificationField Detect Method HSYNC# VCTL1 Short and Long Field DetectVideo Input Filtering Vclkin VSYNC# VCTL2 Scaling Operation 10. Input Filter Mode SelectionInput Filter Modes Chrominance Re-sampling Operation 2 Scaled Co-Sited Filtering Edge Pixel Replication 11. Edge Pixel Replication Ancillary Data Capture Raw Data Capture Notification Raw Data Capture ModeHorizontal Ancillary Hanc Data Capture Vertical Ancillary Vanc Data Capture Raw Data Fifo Packing 11. Raw Data Mode Capture OperationFrmc TCI Capture Features TCI Capture ModeTCI Data Capture Synchronizing the System Clock TCI Capture Error DetectionPCR Clear Frmc 12. TCI Capture Mode OperationTCI Data Capture Notification Vcactl Bit Reading from the Fifo Writing to the FifoPerr Psterr Capture Line Boundary Conditions Capturing Video in BT.656 or Y/C Mode Capturing Video in Raw Data Mode Handling Fifo Overrun in BT.656 or Y/C Mode Capturing Data in TCI Capture Mode Handling Fifo Overrun Condition in Raw Data Mode Video Capture Registers Handling Fifo Overrun Condition in TCI Capture Mode13. Video Capture Control Registers Fsync Frmc F2C F1C Vcypos Video Capture Channel x Status Register VCASTAT, VcbstatVcfld Vcxpos Video Capture Channel a Control Register Vcactl BT.656 or Y/C Mode Raw Data Mode TCI ModeDescription Bit Lfde Sfde Resmpl None ResetRstch Blkcap Rdfe Finv EXC Fldd Vrst Hrst Vcen V0EAV Eavsav ExternEavfid FDL V1EAV Video Capture Channel x Field 1 Start Register VCxSTRT1 Value BT.656 or Y/C Mode Raw Data Mode TCI Mode Video Capture Channel x Field 1 Stop Register VCxSTOP1 Vcystop Video Capture Channel x Field 2 Start Register VCxSTRT2Vcxstop 26. Video Capture Channel x Field 2 Stop Register VCxSTOP2 Video Capture Channel x Field 2 Stop Register VCxSTOP2 Video Capture Channel x Vertical Interrupt Register VCxVINT VCTHRLD1 VCTHRLD2 CAPEVTCT1 Video Capture Channel x Event Count Register VCxEVTCTVideo Capture Channel B Control Register Vcbctl CAPEVTCT2 Vrst Hrst Vcen 30. Video Capture Channel B Control Register Vcbctl SAV or VCTL1 inactive edge Not used TCI Capture Control Register Tcictl BT.656, Y/C Mode, or Raw Data Mode TCI Mode24. TCI Capture Control Register Tcictl Field Descriptions Inpcr TCI Clock Initialization LSB Register Tciclkinitl TCI Clock Initialization MSB Register Tciclkinitm Bit Value ModeTCI System Time Clock LSB Register Tcistclkl Pcre Default PcrmTCI System Time Clock MSB Register Tcistclkm Pcre Pcrm TCI System Time Clock Compare MSB Register Tcistcmpm TCI System Time Clock Compare LSB Register TcistcmplATC Atcm Value BT.656, Y/C Mode, or Raw Data Mode TCI ModeTCI System Time Clock Compare Mask LSB Register Tcistmskl TCI System Time Clock Compare Mask MSB Register Tcistmskm TCI System Time Clock Ticks Interrupt Register Tciticks Value BT.656, Y/C Mode, or Raw Data Mode TCI M odeTickct 35. Video Capture Fifo Registers Function Capture Mode Register BT.656 or Y/C Raw DataVideo Capture Fifo Registers 34. Video Capture Fifo Registers Video Display Field and Frame Operation Displaying Video in BT.656 or Y/C ModeVideo Display Registers Recommended Values Image Timing Video Display Mode SelectionVideo Display Mode Selection Dmode Bits Mode Description Smpte 296M Compatible Progressive Scan Display Interlaced Blanking Intervals and Video Areas Progressive Blanking Intervals and Video Area Video Display Counters Horizontal Blanking and Horizontal Sync Timing Port Sync Operation Sync Signal GenerationBT.656 Video Display Mode External Sync Operation Fpcount Vclkout Display Timing Reference Codes 525/60 Description BT.656 Frame TimingLine Number Line Number Vclkout Blanking Codes3 BT.656 Image Display 4 BT.656 Fifo Unpacking 3 Y/C Image Display Y/C Video Display Mode1 Y/C Display Timing Reference Codes 2 Y/C Blanking Codes Output Filter Modes Output Filter Mode Selection4 Y/C Fifo Unpacking Video Output Filtering 2x Co-Sited Scaling 15. Chrominance Re-sampling 18. Output Edge Pixel Replication 2x Interspersed Scaling Vertical Ancillary Vanc Data Display Raw Data Display ModeAncillary Data Display Horizontal Ancillary Hanc Data Display Raw Data Fifo Unpacking Raw Mode RGB Output Support Vdctl Bit Video Display Field and Frame OperationDisplay Determination and Notification Display Operation Display Line Boundary Conditions Video Display Event Generation Yfifo Display Timing ExamplesInterlaced BT.656 Timing Example Ipcount =IMGSIZE78 Flcount Vclkin Fpcount Ipcount VCTL1 Hblnkac VCTL1 Hsyncac VclkoutFrmwidth = IMGHOFF1 = 112 26. BT.656 Interlaced Display Vertical Timing Example Interlaced Raw Display Example Ipcount VCTL1 Hblnkab Vclkin FpcountVCTL1 Hsyncab Vclkout 28. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example Frmwidth = IMGHOFF1 = Hblnkstart = VCTL1 Hblnkac VCTL1 Hsyncac VclkoutHsyncstart = 1350 Hsyncstop = Flcount EAV Ilcount V F 30. Y/C Progressive Display Vertical Timing Example Displaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Handling Under-run Condition of the Display Fifo Video Display Status Register Vdstat Video Display RegistersVideo Display Control Registers Video Display Status Register Vdstat Field Descriptions Video Display Control Register Vdctl Video Display Control Register Vdctl Field Descriptions BT.656 and Y/C Mode Raw Data Mode Video Display Control Register Vdctl Field Descriptions None Flddis Value BT.656 and Y/C Mode Raw Data ModeBlanking None Frmdis Frmwidth Video Display Frame Size Register VdfrmszVideo Display Horizontal Blanking Register Vdhblnk Frmheight Field has no effect BT.656 and Y/C Mode Raw Data Mode 31-28 Reserved VBLNKXSTOP1 VBLNKYSTOP1 VBLNKXSTART2 VBLNKYSTART2 VBLNKXSTOP2 Value BT.656 and Y/C ModeDEFAULT0 VBLNKYSTOP2 None Negoff Video Display Field 1 Image Offset Register VDIMGOFF1IMGVOFF1 IMGHOFF1 IMGVSIZE1 Video Display Field 1 Image Size Register VDIMGSZ1IMGHSIZE1 IMGVOFF2 Video Display Field 2 Image Offset Register VDIMGOFF2IMGHOFF2 IMGHSIZE2 Video Display Field 2 Image Size Register VDIMGSZ2Video Display Field 1 Timing Register VDFLDT1 IMGVSIZE2 FLD2YSTART Video Display Field 2 Timing Register VDFLDT2FLD1YSTART FLD1XSTART VDTHRLD1 Video Display Threshold Register VdthrldVDTHRLD2 Incpix Hsyncstop Video Display Horizontal Synchronization Register VdhsyncHsyncstart VSYNCXSTOP1 VSYNCXSTART1VSYNCYSTART1 VSYNCYSTOP1 VSYNCYSTART2 VSYNCXSTART2 Crld Video Display Counter Reload Register VdreloadVrld Crld Hrld DISPEVT1 Video Display Event Register VddispevtVideo Display Clipping Register Vdclip DISPEVT2 Clipchigh Video Display Default Display Value Register Vddefval Crdefval Video Display Vertical Interrupt Register VdvintCrdefval Cbdefval Defval 56. Video Display Vertical Interrupt Register Vdvint Video Display Field Bit Register Vdfbit VBITSET1 FbitsetFbitclr VBITCLR1 VBITSET2 VBITCLR2 34. Video Display Register Recommended Values Video Display Registers Recommended ValuesRegister Field 525/60 Value 36. Video Display Fifo Registers Function Display ModeVideo Display Fifo Registers 35. Video Display Fifo Registers General-Purpose I/O Operation Video Port Registers Gpio RegistersOffset Address Acronym Register Name Class Video Port Peripheral Identification Register VppidType Class Revision Stop Video Port Peripheral Control Register PCRPeren Soft Free Peren Video Port Pin Function Register Pfunc Field Descriptions Video Port Pin Function Register Pfunc Normal VDATA0TO9 Normal VDATA10TO19 Video Port Pin Direction Register Pdir Field Descriptions Video Port Pin Direction Register Pdir VDATA0T32IN VDATA0T32OUT VDATA12TO15IN VDATA12TO15OUTVDATA8TO9IN VDATA8TO9OUT VDATA4TO7IN VDATA4TO7OUT Video Port Pin Data Input Register Pdin Field Descriptions Video Port Pin Data Input Register Pdin PDOUT22 Video Port Pin Data Output Register PdoutVideo Port Pin Data Out Register Pdout Field Descriptions PDOUT9 PDOUT8 PDOUT7 PDOUT6 PDOUT5 PDOUT4 PDOUT3 PDOUT2 When writing data, writes to PDOUT20 bit Video Port Pin Data Set Register Pdset Field Descriptions Video Port Pin Data Set Register Pdset Video Port Pin Data Clear Register Pdclr Field Descriptions Video Port Pin Data Clear Register Pdclr PIEN9 PIEN8 PIEN7 PIEN6 PIEN5 PIEN4 PIEN3 PIEN2 Video Port Pin Interrupt Enable Register PienPIEN22 Value Description Video Port Pin Interrupt Polarity Register Pipol None VCTL2INT Video Port Pin Interrupt Status Register PistatPISTAT22 None VCTL3INT PICLR9 PICLR8 PICLR7 PICLR6 PICLR5 PICLR4 PICLR3 PICLR2 Video Port Pin Interrupt Clear Register PiclrPICLR22 Vcxo Interpolated Control Port Interface VIC Port Interface SignalsVIC Port Signal Direction Description Overview Example Values for Interpolation Rate Operational Details VIC Port Registers Enabling VIC PortVIC Port Registers VIC Control Register Vicctl Field Descriptions VIC Control Register Vicctl VIC Input Register Vicin Field Descriptions VIC Input Register VicinVicinbits VIC Clock Divider Register Vicdiv Field Descriptions VIC Clock Divider Register VicdivVicclkdiv DSP Products ApplicationsRfid