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Texas Instruments TMS320DM648 manual Overview, VIC Port Interface Signals

Models: TMS320DM648

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Overview

6.1Overview

The VCXO interpolated control (VIC) port provides single-bit interpolated VCXO control with resolution from 9 bits to up to 16 bits. The frequency of interpolation is dependent on the resolution needed.

When the video port is used in transport stream interface (TCI) mode, the VIC port is used to control the system clock, VCXO, for MPEG transport stream (Figure 6-1).

The VIC port supports following features:

∙Single-bit interpolated VCXO control

∙Programmable precision from 9 to 16 bits

Figure 6-1. TCI System Block Diagram

		VDATA[7−0](TSIdatain)
		VCLK1(TSIclock)	Satellite/
		VCLK1(TSIclock)	cable
Video		VCTL1(CAPENA)	cable
Video		VCTL1(CAPENA)	decoder
port A			decoder
port A		VCTL2(PACSTRT)	with
		VCTL2(PACSTRT)	with
		VCTL3(PACERR)	FEC
		VCTL3(PACERR)
		5VDC
DSP
		2.2k Ω
			VCXO
			27MHz
	VDAC	22k Ω	0.1
VIC	VDAC

			mF
			mF
		100pF
	STCLK

6.2Interface

The pin list for VIC port is shown in Table 6-1(pins are 3.3V I/Os).

Table 6-1. VIC Port Interface Signals

VIC Port Signal	Direction	Description
VDAC	Output	VCXO control
STCLK	Input	System time clock

168

VCXO Interpolated Control Port

SPRUEM1 –May 2007

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Texas Instruments TMS320DM648 manual Overview, VIC Port Interface Signals, VIC Port Signal Direction Description

Contents

Users Guide Submit Documentation Feedback Contents Raw Data Capture Mode BT.656 Image Display Video Display Registers Recommended Values Operational Details List of Figures Bit BT.656 Fifo Unpacking Video Display Event Register Vddispevt List of Tables Video Display Register Recommended Values About This Manual Notational ConventionsRelated Documentation From Texas Instruments Related Documentation From Texas Instruments Trademarks Overview Video Port Video Port Block Diagram Video Port Fifo Edma InterfaceVideo Capture Fifo Configurations BT.656 Video Capture Fifo ConfigurationYsrca Y/C Video Capture Fifo Configuration Video Display Fifo Configurations Bit Raw Video Capture Fifo ConfigurationBit Locked Raw Video Display Fifo Configuration 10. Y/C Video Display Fifo Configuration Video Port RegistersVideo Capture Signal Mapping1 Video Display Signal MappingVideo Port Pin Mapping Capture Mode BT.656 Raw Data Data Bus Bit Vdin Bus Usage for Capture ModesVdin Data Bus Usage for Capture Modes1 Vdout Data Bus Usage for Display Modes Video Port Pin MultiplexingVideoPort Clocking Vdout Data Bus Usage for Display Modes1Video Port Reset Operation Power-On ResetPeripheral Bus Reset Software Port ResetCapture Channel Reset Display Channel ResetInterrupt Operation Edma Operation Capture Edma Event GenerationDisplay Edma Event Generation Edma Size and Threshold RestrictionsEdma Interface Operation Video Port Control RegistersVideo Port Control Registers Acronym Register NameVideo Port Control Register Vpctl Video Port Control Register Vpctl Field DescriptionsDescription Video Port Operating Mode Selection Operating ModeVideo Port Status Register Vpstat Video Port Status Register Vpstat Field DescriptionsVideo Port Interrupt Enable Register Vpie Dcna LfdaVideo Port Interrupt Status Register Vpis Lfda Sfda VINTA2 VINTA1 Serra Ccmpa CovraVideo Port Interrupt Status Register Vpis Field Descriptions None Clear VdctlShort field detected on channel a interrupt detected bit Covra BT.656 and Y/C Mode Field and Frame Operation Video Capture PortVideo Capture Mode Selection BT.656 Video Capture ModeVideo Capture Mode Selection 1 BT.656 Capture ChannelsError Correction by Protection Bits BT.656 Protection Bits3 BT.656 Image Window and Capture Video Capture Parameters4 BT.656 Data Sampling 5 BT.656 Fifo PackingCommon Video Source Parameters Video SourceY/C Video Capture Mode 1 Y/C Capture Channels2 Y/C Timing Reference Codes 3 Y/C Image Window and CaptureBT.656 and Y/C Mode Field and Frame Operation 4 Y/C Fifo PackingBit Y/C Fifo Packing VclkinaBT.656 and Y/C Mode Capture Operation Capture Determination and NotificationVC xCTL Bit OperationVertical Counter Reset Point Vertical SynchronizationVertical Synchronization Programming EAVVcount Operation Example EXC = VRST=0 VRST=1 FINV=0 FINV=1 VcountHorizontal Counter Reset Point Horizontal SynchronizationHorizontal Synchronization Programming VCxCTL BitField Identification Field Identification ProgrammingField Detect Method Short and Long Field Detect Video Input FilteringVclkin VSYNC# VCTL2 HSYNC# VCTL110. Input Filter Mode Selection Input Filter ModesChrominance Re-sampling Operation Scaling OperationEdge Pixel Replication 2 Scaled Co-Sited FilteringAncillary Data Capture 11. Edge Pixel ReplicationRaw Data Capture Mode Horizontal Ancillary Hanc Data CaptureVertical Ancillary Vanc Data Capture Raw Data Capture Notification11. Raw Data Mode Capture Operation Raw Data Fifo PackingFrmc TCI Capture Mode TCI Capture FeaturesTCI Data Capture TCI Capture Error Detection Synchronizing the System ClockPCR 12. TCI Capture Mode Operation TCI Data Capture NotificationVcactl Bit Clear FrmcWriting to the Fifo Reading from the FifoPerr Psterr Capturing Video in BT.656 or Y/C Mode Capture Line Boundary ConditionsHandling Fifo Overrun in BT.656 or Y/C Mode Capturing Video in Raw Data ModeHandling Fifo Overrun Condition in Raw Data Mode Capturing Data in TCI Capture ModeHandling Fifo Overrun Condition in TCI Capture Mode Video Capture Registers13. Video Capture Control Registers Video Capture Channel x Status Register VCASTAT, Vcbstat Fsync Frmc F2C F1C VcyposVcfld Vcxpos BT.656 or Y/C Mode Raw Data Mode TCI Mode Video Capture Channel a Control Register VcactlDescription Bit None Reset Rstch BlkcapRdfe Finv EXC Fldd Vrst Hrst Vcen Lfde Sfde ResmplEavsav Extern Eavfid FDLV1EAV V0EAVValue BT.656 or Y/C Mode Raw Data Mode TCI Mode Video Capture Channel x Field 1 Start Register VCxSTRT1Video Capture Channel x Field 1 Stop Register VCxSTOP1 Video Capture Channel x Field 2 Start Register VCxSTRT2 VcystopVcxstop Video Capture Channel x Field 2 Stop Register VCxSTOP2 26. Video Capture Channel x Field 2 Stop Register VCxSTOP2Video Capture Channel x Vertical Interrupt Register VCxVINT VCTHRLD2 VCTHRLD1Video Capture Channel x Event Count Register VCxEVTCT Video Capture Channel B Control Register VcbctlCAPEVTCT2 CAPEVTCT130. Video Capture Channel B Control Register Vcbctl Vrst Hrst VcenSAV or VCTL1 inactive edge Not used BT.656, Y/C Mode, or Raw Data Mode TCI Mode TCI Capture Control Register Tcictl24. TCI Capture Control Register Tcictl Field Descriptions TCI Clock Initialization LSB Register Tciclkinitl InpcrBit Value Mode TCI Clock Initialization MSB Register TciclkinitmTCI System Time Clock LSB Register Tcistclkl Default Pcrm TCI System Time Clock MSB Register TcistclkmPcre Pcrm PcreTCI System Time Clock Compare LSB Register Tcistcmpl TCI System Time Clock Compare MSB Register TcistcmpmATC Value BT.656, Y/C Mode, or Raw Data Mode TCI Mode TCI System Time Clock Compare Mask LSB Register TcistmsklTCI System Time Clock Compare Mask MSB Register Tcistmskm AtcmValue BT.656, Y/C Mode, or Raw Data Mode TCI M ode TCI System Time Clock Ticks Interrupt Register TciticksTickct Capture Mode Register BT.656 or Y/C Raw Data Video Capture Fifo Registers34. Video Capture Fifo Registers 35. Video Capture Fifo Registers FunctionDisplaying Video in BT.656 or Y/C Mode Video Display Field and Frame OperationVideo Display Registers Recommended Values Video Display Mode Selection Video Display Mode SelectionDmode Bits Mode Description Image TimingSmpte 296M Compatible Progressive Scan Display Interlaced Blanking Intervals and Video Areas Video Display Counters Progressive Blanking Intervals and Video AreaHorizontal Blanking and Horizontal Sync Timing Sync Signal Generation BT.656 Video Display ModeExternal Sync Operation Port Sync OperationDisplay Timing Reference Codes Fpcount VclkoutBT.656 Frame Timing Line NumberLine Number 525/60 DescriptionBlanking Codes 3 BT.656 Image Display4 BT.656 Fifo Unpacking VclkoutY/C Video Display Mode 1 Y/C Display Timing Reference Codes2 Y/C Blanking Codes 3 Y/C Image DisplayOutput Filter Mode Selection 4 Y/C Fifo UnpackingVideo Output Filtering Output Filter Modes15. Chrominance Re-sampling 2x Co-Sited Scaling2x Interspersed Scaling 18. Output Edge Pixel ReplicationRaw Data Display Mode Ancillary Data DisplayHorizontal Ancillary Hanc Data Display Vertical Ancillary Vanc Data DisplayRaw Mode RGB Output Support Raw Data Fifo UnpackingVideo Display Field and Frame Operation Display Determination and NotificationDisplay Operation Vdctl BitVideo Display Event Generation Display Line Boundary ConditionsDisplay Timing Examples Interlaced BT.656 Timing ExampleIpcount =IMGSIZE78 YfifoVclkin Fpcount Ipcount VCTL1 Hblnkac VCTL1 Hsyncac Vclkout FlcountFrmwidth = IMGHOFF1 = 112 Interlaced Raw Display Example 26. BT.656 Interlaced Display Vertical Timing ExampleVclkin Fpcount Ipcount VCTL1 HblnkabVCTL1 Hsyncab Vclkout 28. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example VCTL1 Hblnkac VCTL1 Hsyncac Vclkout Frmwidth = IMGHOFF1 = Hblnkstart =Hsyncstart = 1350 Hsyncstop = 30. Y/C Progressive Display Vertical Timing Example Flcount EAV Ilcount V FDisplaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Handling Under-run Condition of the Display Fifo Video Display Registers Video Display Status Register VdstatVideo Display Control Registers Video Display Control Register Vdctl Video Display Status Register Vdstat Field DescriptionsBT.656 and Y/C Mode Raw Data Mode Video Display Control Register Vdctl Field DescriptionsVideo Display Control Register Vdctl Field Descriptions Value BT.656 and Y/C Mode Raw Data Mode BlankingNone Frmdis None FlddisVideo Display Frame Size Register Vdfrmsz Video Display Horizontal Blanking Register VdhblnkFrmheight FrmwidthBT.656 and Y/C Mode Raw Data Mode 31-28 Reserved Field has no effectVBLNKYSTOP1 VBLNKXSTOP1VBLNKYSTART2 VBLNKXSTART2Value BT.656 and Y/C Mode DEFAULT0VBLNKYSTOP2 VBLNKXSTOP2Video Display Field 1 Image Offset Register VDIMGOFF1 IMGVOFF1IMGHOFF1 None NegoffVideo Display Field 1 Image Size Register VDIMGSZ1 IMGVSIZE1IMGHSIZE1 Video Display Field 2 Image Offset Register VDIMGOFF2 IMGVOFF2IMGHOFF2 Video Display Field 2 Image Size Register VDIMGSZ2 Video Display Field 1 Timing Register VDFLDT1IMGVSIZE2 IMGHSIZE2Video Display Field 2 Timing Register VDFLDT2 FLD1YSTARTFLD1XSTART FLD2YSTARTVideo Display Threshold Register Vdthrld VDTHRLD2Incpix VDTHRLD1Video Display Horizontal Synchronization Register Vdhsync HsyncstopHsyncstart VSYNCXSTART1 VSYNCYSTART1VSYNCYSTOP1 VSYNCXSTOP1VSYNCXSTART2 VSYNCYSTART2Video Display Counter Reload Register Vdreload VrldCrld Hrld CrldVideo Display Event Register Vddispevt Video Display Clipping Register VdclipDISPEVT2 DISPEVT1Video Display Default Display Value Register Vddefval ClipchighVideo Display Vertical Interrupt Register Vdvint Crdefval CbdefvalDefval CrdefvalVideo Display Field Bit Register Vdfbit 56. Video Display Vertical Interrupt Register VdvintFbitset FbitclrVBITCLR1 VBITSET1VBITCLR2 VBITSET2Video Display Registers Recommended Values 34. Video Display Register Recommended ValuesRegister Field 525/60 Value Display Mode Video Display Fifo Registers35. Video Display Fifo Registers 36. Video Display Fifo Registers FunctionGeneral-Purpose I/O Operation Gpio Registers Video Port RegistersOffset Address Acronym Register Name Video Port Peripheral Identification Register Vppid TypeClass Revision ClassVideo Port Peripheral Control Register PCR Peren Soft FreePeren StopVideo Port Pin Function Register Pfunc Video Port Pin Function Register Pfunc Field DescriptionsNormal VDATA10TO19 Normal VDATA0TO9Video Port Pin Direction Register Pdir Video Port Pin Direction Register Pdir Field DescriptionsVDATA12TO15IN VDATA12TO15OUT VDATA8TO9IN VDATA8TO9OUTVDATA4TO7IN VDATA4TO7OUT VDATA0T32IN VDATA0T32OUTVideo Port Pin Data Input Register Pdin Video Port Pin Data Input Register Pdin Field DescriptionsVideo Port Pin Data Output Register Pdout Video Port Pin Data Out Register Pdout Field DescriptionsPDOUT9 PDOUT8 PDOUT7 PDOUT6 PDOUT5 PDOUT4 PDOUT3 PDOUT2 PDOUT22When writing data, writes to PDOUT20 bit Video Port Pin Data Set Register Pdset Video Port Pin Data Set Register Pdset Field DescriptionsVideo Port Pin Data Clear Register Pdclr Video Port Pin Data Clear Register Pdclr Field DescriptionsVideo Port Pin Interrupt Enable Register Pien PIEN9 PIEN8 PIEN7 PIEN6 PIEN5 PIEN4 PIEN3 PIEN2PIEN22 Video Port Pin Interrupt Polarity Register Pipol Value DescriptionVideo Port Pin Interrupt Status Register Pistat PISTAT22None VCTL3INT None VCTL2INTVideo Port Pin Interrupt Clear Register Piclr PICLR9 PICLR8 PICLR7 PICLR6 PICLR5 PICLR4 PICLR3 PICLR2PICLR22 Vcxo Interpolated Control Port VIC Port Interface Signals VIC Port Signal Direction DescriptionOverview InterfaceOperational Details Example Values for Interpolation RateEnabling VIC Port VIC Port RegistersVIC Port Registers VIC Control Register Vicctl VIC Control Register Vicctl Field DescriptionsVIC Input Register Vicin VIC Input Register Vicin Field DescriptionsVicinbits VIC Clock Divider Register Vicdiv VIC Clock Divider Register Vicdiv Field DescriptionsVicclkdiv Products Applications DSPRfid