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Display Timing Examples
The interlaced BT.656 vertical output timing is shown in Figure
The VBLNK and VSYNC signals are shown as they would be output for
The FLD output is setup to transition at the start of each analog field (start of vertical blanking). Since EAV[F] transitions on lines 4 and 266, this requires programming FBITCLR to 4, FBITSET to 266, FLD1YSTART to 1, and FLD2YSTART to 263. Note that FLD2XSTRT is 360 so that the field indicator output changes halfway through the line.
The ILCOUNT operation follows the description in Section 4.1.2. ILCOUNT resets to 1 at the first displayed line (FLCOUNT = VBLNKSTOPx + IMGVOFFx) and stops counting at the last displayed pixel (IPCOUNT = IMGVSIZEx). The operation during
The active horizontal output column shows the output data during the active portion of the horizontal line. It is assumed that the DVEN bit in VDCTL is set to enable the default output.
112 | Video Display Port | SPRUEM1 |