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Displaying Video in Raw Data Mode
22.Wait for 2 or more frame times, to allow the display counters and control signals to become properly synchronized.
23.Write to VDCTL to clear the BLKDIS bit.
24.Display is enabled at the start of the first frame after BLKDIS = 0 and begins with the first selected field. EDMA events are generated as triggered by VDTHRLD and the DEVTCT counter. When a selected field has been displayed (FLCOUNT = FRMHEIGHT and FPCOUNT = FRMWIDTH), the appropriate F1D, F2D, or FRMD bits are set and cause the DCMP bit in VPIS to be set. This generates a DSP interrupt, if the DCMP bit is enabled in VPIE.
25.If continuous display is enabled, the video port begins displaying again at the start of the next field or frame. If noncontinuous field 1 and field 2 or frame display is enabled, the next field or frame is displayed, during which the DSP must clear the appropriate completion status bit or a DCNA interrupt occurs and incorrect data may be output.
4.11Displaying Video in Raw Data Mode
In order to display video in the raw data mode, the following steps are needed:
1.To use the desired Video Port, program the Pin Mux Register (PINMUX) appropriately to ensure that the multiplexed pins work as Video Port Pins. Refer to the
2.Program the VPx_CTL Register appropriately to use the desired Video Port as a Display Port.
3.Set the PEREN bit in the video port peripheral control register (PCR).
4.Set the frame size in VDFRMSZ. Set the number of lines per frame (FRMHIGHT) and the number of pixels per line (FRMWIDTH).
5.Set the horizontal blanking in VDHBLNK. Specify the frame pixel counter value where horizontal blanking starts (HBLNKSTART) and pixel location where horizontal blanking stops (HBLNKSTOP).
6.Set the vertical blanking start for field 1 in VDVBLKS1. Specify the frame line (VBLNKYSTART1) and frame pixel counter (VBLNKXSTART1) values for the pixel where vertical blanking starts for field 1.
7.Set the vertical blanking end for field 1 in VDVBLKE1. Specify the frame line (VBLNKYSTOP1) and frame pixel counter (VBLNKXSTOP1) values for the pixel where vertical blanking ends for field 1.
8.Set VDIMGSZn. Adjust the displayed image size by setting the HSIZE and VSIZE bits.
9.Set VDIMOFF. Adjust the displayed image offset within the active video area (by setting HOFFSET and VOFFSET).
10.Set the vertical blanking start for field 2 in VDVBLKS2. Specify the frame line (VBLNKYSTART2) and frame pixel counter (VBLNKXSTART2) values for the pixel where vertical blanking starts for field 2.
11.Set the vertical blanking end for field 2 in VDVBLKE2. Specify the frame line (VBLNKYSTOP2) and frame pixel counter (VBLNKXSTOP2) values for the pixel where vertical blanking ends for field 2.
12.Set the vertical synchronization start for field 1 in VDVSYNS1. Specify the frame line (VSYNCYSTART1) and frame pixel counter (VSYNCXSTART1) values for the pixel where vertical synchronization starts for field 1.
13.Set the vertical synchronization end for field 1 in VDVSYNE1. Specify the frame line (VSYNCYSTOP1) and frame pixel counter (VSYNCXSTOP1) values for the pixel where vertical synchronization ends for field 1.
14.Set the vertical synchronization start for field 2 in VDVSYNS2. Specify the frame line (VSYNCYSTART2) and frame pixel counter (VSYNCXSTART2) values for the pixel where vertical synchronization starts for field 2.
15.Set the vertical synchronization end for field 2 in VDVSYNE2. Specify the frame line (VSYNCYSTOP2) and frame pixel counter (VSYNCXSTOP2) values for the pixel where vertical synchronization ends for field 2.
16.Set the horizontal synchronization in VDHSYNC. Specify the frame pixel counter value for a pixel where HSYNC gets asserted (HSYNCYSTART) and width of the HSYNC pulse (HSYNCSTOP) in frame pixel clocks.
17.Set the video display field 2 timing. Specify the first line and pixel of field 2 in VDFLDT2.
18.Configure a EDMA to move data from table in the DSP memory to YDSTA
19.Set DISPEVT1 and DISPEVT2 bits in VDDISPEVT. Event count is total double words per field divided
120 | Video Display Port | SPRUEM1 |
