Enabling VIC Port | Texas Instruments TMS320DM648 manual

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Enabling VIC Port

6.4Enabling VIC Port

Perform the following steps to enable the VIC port.

1.Clear the GO bit in the VIC control register (VICCTL) to 0.

2.Set the PRECISION bits in VICCTL to the desired precision.

3.Set the VIC clock divider register (VICDIV) bits to appropriate value based on the precision and interpolation frequency.

4.Set the GO bit in VICCTL to 1.

5.The VIC input register (VICIN) is written into every time a new input code is available for interpolation. Repeat step Step 1 as often as needed.

6.5VIC Port Registers

The VIC port registers are listed in Table 6-3. See the device-specific datasheet for the memory address of these registers.

Table 6-3. VIC Port Registers

Offset
Address (1)	Acronym	Register Name	Section
00h	VICCTL	VIC Control Register	Section 6.5.1
04h	VICIN	VIC Input Register	Section 6.5.2
08h	VICDIV	VIC Clock Divider Register	Section 6.5.3

(1)The absolute address of the registers is device specific and is equal to the base address + offset address. See the device-specific datasheet to verify the register addresses.

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VCXO Interpolated Control Port

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Texas Instruments TMS320DM648 manual Enabling VIC Port, VIC Port Registers

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Users Guide Submit Documentation Feedback Contents Raw Data Capture Mode BT.656 Image Display Video Display Registers Recommended Values Operational Details List of Figures Bit BT.656 Fifo Unpacking Video Display Event Register Vddispevt List of Tables Video Display Register Recommended Values Related Documentation From Texas Instruments About This ManualNotational Conventions Related Documentation From Texas Instruments Trademarks Overview Video Port Video Port Block Diagram Video Port Fifo Edma Interface Video Capture Fifo Configurations BT.656 Video Capture Fifo Configuration Ysrca Y/C Video Capture Fifo Configuration Video Display Fifo Configurations Bit Raw Video Capture Fifo Configuration Bit Locked Raw Video Display Fifo Configuration 10. Y/C Video Display Fifo Configuration Video Port Registers Video Port Pin Mapping Video Capture Signal Mapping1Video Display Signal Mapping Vdin Data Bus Usage for Capture Modes1 Capture Mode BT.656 Raw Data Data Bus BitVdin Bus Usage for Capture Modes VideoPort Clocking Vdout Data Bus Usage for Display ModesVideo Port Pin Multiplexing Vdout Data Bus Usage for Display Modes1 Video Port Peripheral Bus Reset Reset OperationPower-On Reset Software Port Reset Interrupt Operation Capture Channel ResetDisplay Channel Reset Edma Operation Capture Edma Event Generation Display Edma Event Generation Edma Size and Threshold Restrictions Video Port Control Registers Edma Interface OperationVideo Port Control Registers Acronym Register Name Description Video Port Control Register VpctlVideo Port Control Register Vpctl Field Descriptions Video Port Operating Mode Selection Operating Mode Video Port Status Register Vpstat Video Port Status Register Vpstat Field Descriptions Video Port Interrupt Enable Register Vpie Dcna Lfda Video Port Interrupt Status Register Vpis Lfda Sfda VINTA2 VINTA1 Serra Ccmpa Covra Video Port Interrupt Status Register Vpis Field Descriptions None Clear Vdctl Short field detected on channel a interrupt detected bit Covra BT.656 and Y/C Mode Field and Frame Operation Video Capture Port Video Capture Mode Selection Video Capture Mode SelectionBT.656 Video Capture Mode 1 BT.656 Capture Channels Error Correction by Protection Bits BT.656 Protection Bits 3 BT.656 Image Window and Capture Video Capture Parameters Common Video Source Parameters 4 BT.656 Data Sampling5 BT.656 Fifo Packing Video Source 2 Y/C Timing Reference Codes Y/C Video Capture Mode1 Y/C Capture Channels 3 Y/C Image Window and Capture Bit Y/C Fifo Packing BT.656 and Y/C Mode Field and Frame Operation4 Y/C Fifo Packing Vclkina VC xCTL Bit BT.656 and Y/C Mode Capture OperationCapture Determination and Notification Operation Vertical Synchronization Programming Vertical Counter Reset PointVertical Synchronization EAV Vcount Operation Example EXC = VRST=0 VRST=1 FINV=0 FINV=1 Vcount Horizontal Synchronization Programming Horizontal Counter Reset PointHorizontal Synchronization VCxCTL Bit Field Detect Method Field IdentificationField Identification Programming Vclkin VSYNC# VCTL2 Short and Long Field DetectVideo Input Filtering HSYNC# VCTL1 Chrominance Re-sampling Operation 10. Input Filter Mode SelectionInput Filter Modes Scaling Operation Edge Pixel Replication 2 Scaled Co-Sited Filtering Ancillary Data Capture 11. Edge Pixel Replication Vertical Ancillary Vanc Data Capture Raw Data Capture ModeHorizontal Ancillary Hanc Data Capture Raw Data Capture Notification Frmc 11. Raw Data Mode Capture OperationRaw Data Fifo Packing TCI Data Capture TCI Capture ModeTCI Capture Features PCR TCI Capture Error DetectionSynchronizing the System Clock Vcactl Bit 12. TCI Capture Mode OperationTCI Data Capture Notification Clear Frmc Perr Psterr Writing to the FifoReading from the Fifo Capturing Video in BT.656 or Y/C Mode Capture Line Boundary Conditions Handling Fifo Overrun in BT.656 or Y/C Mode Capturing Video in Raw Data Mode Handling Fifo Overrun Condition in Raw Data Mode Capturing Data in TCI Capture Mode 13. Video Capture Control Registers Handling Fifo Overrun Condition in TCI Capture ModeVideo Capture Registers Vcfld Vcxpos Video Capture Channel x Status Register VCASTAT, VcbstatFsync Frmc F2C F1C Vcypos Description Bit BT.656 or Y/C Mode Raw Data Mode TCI ModeVideo Capture Channel a Control Register Vcactl Rdfe Finv EXC Fldd Vrst Hrst Vcen None ResetRstch Blkcap Lfde Sfde Resmpl V1EAV Eavsav ExternEavfid FDL V0EAV Value BT.656 or Y/C Mode Raw Data Mode TCI Mode Video Capture Channel x Field 1 Start Register VCxSTRT1 Video Capture Channel x Field 1 Stop Register VCxSTOP1 Vcxstop Video Capture Channel x Field 2 Start Register VCxSTRT2Vcystop Video Capture Channel x Field 2 Stop Register VCxSTOP2 26. Video Capture Channel x Field 2 Stop Register VCxSTOP2 Video Capture Channel x Vertical Interrupt Register VCxVINT VCTHRLD2 VCTHRLD1 CAPEVTCT2 Video Capture Channel x Event Count Register VCxEVTCTVideo Capture Channel B Control Register Vcbctl CAPEVTCT1 30. Video Capture Channel B Control Register Vcbctl Vrst Hrst Vcen SAV or VCTL1 inactive edge Not used 24. TCI Capture Control Register Tcictl Field Descriptions BT.656, Y/C Mode, or Raw Data Mode TCI ModeTCI Capture Control Register Tcictl TCI Clock Initialization LSB Register Tciclkinitl Inpcr TCI System Time Clock LSB Register Tcistclkl Bit Value ModeTCI Clock Initialization MSB Register Tciclkinitm Pcre Pcrm Default PcrmTCI System Time Clock MSB Register Tcistclkm Pcre ATC TCI System Time Clock Compare LSB Register TcistcmplTCI System Time Clock Compare MSB Register Tcistcmpm TCI System Time Clock Compare Mask MSB Register Tcistmskm Value BT.656, Y/C Mode, or Raw Data Mode TCI ModeTCI System Time Clock Compare Mask LSB Register Tcistmskl Atcm Tickct Value BT.656, Y/C Mode, or Raw Data Mode TCI M odeTCI System Time Clock Ticks Interrupt Register Tciticks 34. Video Capture Fifo Registers Capture Mode Register BT.656 or Y/C Raw DataVideo Capture Fifo Registers 35. Video Capture Fifo Registers Function Video Display Registers Recommended Values Displaying Video in BT.656 or Y/C ModeVideo Display Field and Frame Operation Dmode Bits Mode Description Video Display Mode SelectionVideo Display Mode Selection Image Timing Smpte 296M Compatible Progressive Scan Display Interlaced Blanking Intervals and Video Areas Video Display Counters Progressive Blanking Intervals and Video Area Horizontal Blanking and Horizontal Sync Timing External Sync Operation Sync Signal GenerationBT.656 Video Display Mode Port Sync Operation Display Timing Reference Codes Fpcount Vclkout Line Number BT.656 Frame TimingLine Number 525/60 Description 4 BT.656 Fifo Unpacking Blanking Codes3 BT.656 Image Display Vclkout 2 Y/C Blanking Codes Y/C Video Display Mode1 Y/C Display Timing Reference Codes 3 Y/C Image Display Video Output Filtering Output Filter Mode Selection4 Y/C Fifo Unpacking Output Filter Modes 15. Chrominance Re-sampling 2x Co-Sited Scaling 2x Interspersed Scaling 18. Output Edge Pixel Replication Horizontal Ancillary Hanc Data Display Raw Data Display ModeAncillary Data Display Vertical Ancillary Vanc Data Display Raw Mode RGB Output Support Raw Data Fifo Unpacking Display Operation Video Display Field and Frame OperationDisplay Determination and Notification Vdctl Bit Video Display Event Generation Display Line Boundary Conditions Ipcount =IMGSIZE78 Display Timing ExamplesInterlaced BT.656 Timing Example Yfifo Frmwidth = IMGHOFF1 = Vclkin Fpcount Ipcount VCTL1 Hblnkac VCTL1 Hsyncac VclkoutFlcount 112 Interlaced Raw Display Example 26. BT.656 Interlaced Display Vertical Timing Example VCTL1 Hsyncab Vclkout Vclkin FpcountIpcount VCTL1 Hblnkab 28. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example Hsyncstart = 1350 Hsyncstop = VCTL1 Hblnkac VCTL1 Hsyncac VclkoutFrmwidth = IMGHOFF1 = Hblnkstart = 30. Y/C Progressive Display Vertical Timing Example Flcount EAV Ilcount V F Displaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Handling Under-run Condition of the Display Fifo Video Display Control Registers Video Display RegistersVideo Display Status Register Vdstat Video Display Control Register Vdctl Video Display Status Register Vdstat Field Descriptions BT.656 and Y/C Mode Raw Data Mode Video Display Control Register Vdctl Field Descriptions Video Display Control Register Vdctl Field Descriptions None Frmdis Value BT.656 and Y/C Mode Raw Data ModeBlanking None Flddis Frmheight Video Display Frame Size Register VdfrmszVideo Display Horizontal Blanking Register Vdhblnk Frmwidth BT.656 and Y/C Mode Raw Data Mode 31-28 Reserved Field has no effect VBLNKYSTOP1 VBLNKXSTOP1 VBLNKYSTART2 VBLNKXSTART2 VBLNKYSTOP2 Value BT.656 and Y/C ModeDEFAULT0 VBLNKXSTOP2 IMGHOFF1 Video Display Field 1 Image Offset Register VDIMGOFF1IMGVOFF1 None Negoff IMGHSIZE1 Video Display Field 1 Image Size Register VDIMGSZ1IMGVSIZE1 IMGHOFF2 Video Display Field 2 Image Offset Register VDIMGOFF2IMGVOFF2 IMGVSIZE2 Video Display Field 2 Image Size Register VDIMGSZ2Video Display Field 1 Timing Register VDFLDT1 IMGHSIZE2 FLD1XSTART Video Display Field 2 Timing Register VDFLDT2FLD1YSTART FLD2YSTART Incpix Video Display Threshold Register VdthrldVDTHRLD2 VDTHRLD1 Hsyncstart Video Display Horizontal Synchronization Register VdhsyncHsyncstop VSYNCYSTOP1 VSYNCXSTART1VSYNCYSTART1 VSYNCXSTOP1 VSYNCXSTART2 VSYNCYSTART2 Crld Hrld Video Display Counter Reload Register VdreloadVrld Crld DISPEVT2 Video Display Event Register VddispevtVideo Display Clipping Register Vdclip DISPEVT1 Video Display Default Display Value Register Vddefval Clipchigh Defval Video Display Vertical Interrupt Register VdvintCrdefval Cbdefval Crdefval Video Display Field Bit Register Vdfbit 56. Video Display Vertical Interrupt Register Vdvint VBITCLR1 FbitsetFbitclr VBITSET1 VBITCLR2 VBITSET2 Register Field 525/60 Value Video Display Registers Recommended Values34. Video Display Register Recommended Values 35. Video Display Fifo Registers Display ModeVideo Display Fifo Registers 36. Video Display Fifo Registers Function General-Purpose I/O Operation Offset Address Acronym Register Name Gpio RegistersVideo Port Registers Class Revision Video Port Peripheral Identification Register VppidType Class Peren Video Port Peripheral Control Register PCRPeren Soft Free Stop Video Port Pin Function Register Pfunc Video Port Pin Function Register Pfunc Field Descriptions Normal VDATA10TO19 Normal VDATA0TO9 Video Port Pin Direction Register Pdir Video Port Pin Direction Register Pdir Field Descriptions VDATA4TO7IN VDATA4TO7OUT VDATA12TO15IN VDATA12TO15OUTVDATA8TO9IN VDATA8TO9OUT VDATA0T32IN VDATA0T32OUT Video Port Pin Data Input Register Pdin Video Port Pin Data Input Register Pdin Field Descriptions PDOUT9 PDOUT8 PDOUT7 PDOUT6 PDOUT5 PDOUT4 PDOUT3 PDOUT2 Video Port Pin Data Output Register PdoutVideo Port Pin Data Out Register Pdout Field Descriptions PDOUT22 When writing data, writes to PDOUT20 bit Video Port Pin Data Set Register Pdset Video Port Pin Data Set Register Pdset Field Descriptions Video Port Pin Data Clear Register Pdclr Video Port Pin Data Clear Register Pdclr Field Descriptions PIEN22 Video Port Pin Interrupt Enable Register PienPIEN9 PIEN8 PIEN7 PIEN6 PIEN5 PIEN4 PIEN3 PIEN2 Video Port Pin Interrupt Polarity Register Pipol Value Description None VCTL3INT Video Port Pin Interrupt Status Register PistatPISTAT22 None VCTL2INT PICLR22 Video Port Pin Interrupt Clear Register PiclrPICLR9 PICLR8 PICLR7 PICLR6 PICLR5 PICLR4 PICLR3 PICLR2 Vcxo Interpolated Control Port Overview VIC Port Interface SignalsVIC Port Signal Direction Description Interface Operational Details Example Values for Interpolation Rate VIC Port Registers Enabling VIC PortVIC Port Registers VIC Control Register Vicctl VIC Control Register Vicctl Field Descriptions Vicinbits VIC Input Register VicinVIC Input Register Vicin Field Descriptions Vicclkdiv VIC Clock Divider Register VicdivVIC Clock Divider Register Vicdiv Field Descriptions Rfid Products ApplicationsDSP