Texas Instruments TMS320DM648 manual Y/C Video Capture Fifo Configuration

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Video Port FIFO

For Y/C video capture, the FIFO is configured as a single channel split into separate Y, Cb, and Cr buffers with separate write pointers and read registers (YSRCA, CBSRCA, and CRSRCA). Figure 1-4shows how Y data is received on the VDIN[9-2] half of the bus and Cb/Cr data is received on the VDIN[19-12] half of the bus and de-multiplexed into the Cb and Cr buffers.

Figure 1-4. Y/C Video Capture FIFO Configuration

VDIN[9−2]

8

8

VDIN[19−12]

8

Capture FIFO

Y Buffer (2560 bytes)

Cb Buffer (1280 bytes)

Cr Buffer (1280 bytes)

64

64

64

YSRCA

CBSRCA

CRSRCA

22 Overview SPRUEM1 –May 2007

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